Forming a sacrificial liner for dual channel devices
A semiconductor device includes one or more fins. Each fin includes a top channel portion formed from a channel material, a middle portion, and a bottom substrate portion formed from a same material as an underlying substrate. An oxide layer is formed between the bottom substrate portion of each fin and the isolation layer, with a space between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer. A gate dielectric, protruding into the space and in contact with the middle portion, is formed over the one or more fins and has a portion formed from a material different from the oxide layer.
1. A method comprising:
providing a substrate having thereon a layer of epitaxial channel material;
patterning a hardmask above the layer of epitaxial channel material;
performing a first etch to a first depth, using the hardmask as a mask, to form an upper portion of a fin, wherein the first depth extends beyond a bottom surface of the layer of epitaxial channel material;
forming a liner over exposed surfaces of the upper portion of the fin;
performing a second etch to a second depth, using the liner as a mask, to form a lower portion of the fin;
removing the liner; and
forming a gate dielectric on exposed surfaces of the upper portion of the fin, wherein the gate dielectric extends beyond the bottom surface of the layer of epitaxial channel material.
2. The method of claim 1 , further comprising:
oxidizing surfaces of the lower portion of the fin prior to removing the liner from the upper portion of the fin.
3. The method of claim 1 , further comprising:
subsequent to performing the second etch, forming a dielectric material on opposite sides of the fin; and
recessing the dielectric material to a level below the upper surface of the fin.
4. The method of claim 3 , wherein the dielectric material is recessed to a depth above a bottom surface of the liner.
5. The method of claim 1 , wherein the layer of epitaxial channel material comprises silicon.
6. The method of claim 1 , wherein the layer of epitaxial channel material comprises silicon germanium.
7. A method comprising:
providing a substrate having thereon a layer of epitaxial channel material;
patterning a hardmask above the layer of epitaxial channel material;
performing a first etch, using the hardmask as a mask, to form an upper portion of a first fin and an upper portion of a second fin, the first fin adjacent to the second fin, the first etch extending beyond a bottom surface of the layer of epitaxial channel material;
forming a liner over exposed surfaces of the upper portions of the first and second fins;
performing a second etch, using the liner as a mask, to form a lower portion of the first fin and a lower portion of the second fin;
subsequent to performing the second etch, filling gaps between the first fin and the second fin with a dielectric material;
recessing the dielectric material to a level below the upper surfaces of the first and second fins; and
removing the liner,
subsequent to removing the liner, forming a gate dielectric on exposed surfaces of the upper portions of the first and second fins, wherein the gate dielectric extends beyond the bottom surface of the layer of epitaxial channel material.
8. The method of claim 7 , wherein the dielectric material comprises a flowable dielectric.
9. The method of claim 8 , further comprising:
prior to removing the liner, annealing the flowable dielectric.
10. The method of claim 7 , further comprising:
prior to removing the liner, oxidizing side surfaces of the lower portions of the first and second fins.
11. The method of claim 7 , wherein the dielectric material is recessed to a depth above a bottom surface of the liner.
12. A method comprising:
providing a substrate having thereon a first region comprising a layer of first epitaxial channel material and a second region comprising a layer of second epitaxial channel material;
patterning a hardmask above the first and second regions;
performing a first etch, using the hardmask as a mask, to form an upper portion of a first fin comprising the layer of first epitaxial channel material and an upper portion of a second fin comprising the layer of second epitaxial channel material;
forming a liner over exposed surfaces of the upper portions of the first and second fins;
performing a second etch, using the liner as a mask, to form a lower portion of the first fin and a lower portion of the second fin;
subsequent to performing the second etch, filling a gap between the first and second fins with a dielectric material;
recessing the dielectric material to a level below the upper surfaces of the first and second fins; and
removing the liner,
subsequent to removing the liner, forming a gate dielectric on exposed surfaces of the upper portions of the first and second fins, wherein the gate dielectric extends beyond bottom surfaces of the layers of first and second epitaxial channel materials.
13. The method of claim 12 , wherein the dielectric material comprises a flowable dielectric.
14. The method of claim 13 , further comprising:
prior to removing the liner, annealing the flowable dielectric.
15. The method of claim 12 , further comprising:
prior to removing the liner, oxidizing the lower portions of the first and second fins.
16. The method of claim 12 , wherein the dielectric material is recessed to a depth above a bottom surface of the liner.
17. The method of claim 12 , wherein the layer of first epitaxial channel material comprises silicon.
18. The method of claim 12 , wherein the layer of second epitaxial channel material comprises silicon germanium.
19. The method of claim 17 , wherein the first etch extends beyond the bottom surface of the layer of first epitaxial channel material.
20. The method of claim 18 , wherein the first etch extends beyond the bottom surface of the layer of second epitaxial channel material.