Fault injection attack system

1. A fault injection attack method performed by a computing apparatus, the fault injection attack method comprising:

determining a trigger start point in time based on an input signal for a crypto device;

determining a trigger end point in time based on an output signal of the crypto device;

setting a trigger based on the trigger start point in time and the trigger end point in time;

performing a fault injection attack based on the set trigger;

communicating with the crypto device, the crypto device receiving the input signal of the plaintext from the computing apparatus; and

performing the fault injection attack for the crypto device,

wherein the trigger start point in time is determined as a point in time at which a plaintext is input to the crypto device, based on the input signal and the trigger end point in time is determined as a point in time at which a ciphertext is output from the crypto device based on the output signal, so that the trigger is set for an entire encryption operation of the crypto device,

the trigger is set without modifying the internal code of the crypto device based on the connection between the computing apparatus and the crypto device,

wherein a target operation that is a target of the fault injection attack is determined based on an analysis for electromagnetic trace emitted in a process in which the crypto device performs encryption,

wherein the analysis for electromagnetic trace is performed based on a simple power analysis (SPA),

wherein the setting of the trigger comprises setting the trigger based on a jump connection for a connection between the computing apparatus and the crypto device,

wherein the performing of the fault injection attack comprises recovering a secret key based on an XOR operation between a normal ciphertext and a fault-injected erroneous ciphertext,

wherein the recovering comprises recovering the secret key by performing an analysis on a number of all cases related to a position at which a fault is likely to be injected for each fault type,

wherein the fault type is determined based on a position at which a fault is propagated according to an encryption operation.

2. A non-transitory computer-readable record medium storing a program including instructions that cause the computing apparatus to perform the fault injection attack method of claim 1 .

3. A computing apparatus to perform a fault injection attack, the computing apparatus comprising:

a communication interface; and

a processor circuitry,

wherein the processor circuitry is configured to determine a trigger start point in time based on an input signal for a crypto device, determine a trigger end point in time based on an output signal of the crypto device, set a trigger based on the trigger start point in time and the trigger end point in time, and perform a fault injection attack based on the set trigger,

wherein the trigger start point in time is determined as a point in time at which a plaintext is input to the crypto device, based on the input signal and the trigger end point in time is determined as a point in time at which a ciphertext is output from the crypto device based on the output signal, so that the trigger is set for an entire encryption operation of the crypto device, the trigger is set without modifying the internal code of the crypto device based on the connection between the computing apparatus and the crypto device,

wherein a target operation that is a target of the fault injection attack is determined based on an analysis for electromagnetic trace emitted in a process in which the crypto device performs encryption,

wherein the analysis for electromagnetic trace is performed based on a simple power analysis (SPA),

wherein the processor circuitry is configured to set the trigger based on a jump connection for a connection between the computing apparatus and the crypto device,

wherein the processor circuitry is configured to recover a secret key based on an XOR operation between a normal ciphertext and a fault-injected erroneous ciphertext, wherein the processor circuitry is configured to recover the secret key by performing an analysis on a number of all cases related to a position at which a fault is likely to be injected for each fault type,

wherein the fault type is determined based on a position at which a fault is propagated according to an encryption operation,

wherein the processor circuitry is configured to communicate with the crypto device via the communication interface such that the crypto device receives the input signal of the plaintext from the computing apparatus,

wherein the computing apparatus performs the fault injection attack for the crypto device.