System and memory for artificial neural network (ANN) optimization using ANN data locality
A system for an artificial neural network (ANN) includes a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell. The main memory may be configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line. The memory controller may be further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused. Thus, the system optimizes an ANN operation of the processor by utilizing the ANN data locality of the ANN model, which operates at a processor-memory level.
1. A system for an artificial neural network (ANN), the system comprising:
a main memory including a dynamic memory cell electrically coupled to a bit line and a word line; and
a memory controller configured to selectively omit a restore operation during a read operation of the dynamic memory cell and to determine whether data stored in the dynamic memory cell is reused based on an ANN data locality,
wherein data of an output feature map of an ANN model is stored in the dynamic memory cell, and wherein the memory controller is further configured to determine that the output feature map data is not reused during the read operation after the storing of the output feature map data.
2. The system of claim 1 , wherein the dynamic memory cell is configured to operate in a sequence of precharge, access, sense, and restore, or in a sequence of precharge, access, and sense.
3. The system of claim 1 , wherein the main memory is configured to selectively omit the restoration operation during the read operation of the dynamic memory cell by controlling a voltage applied to the word line.
4. The system of claim 1 , wherein the memory controller is further configured to determine whether to perform the restoration operation by determining whether data stored in the dynamic memory cell is reused.
5. The system of claim 1 , wherein a latency of the read operation of the main memory is shorter when the restore operation is omitted than when the restore operation is not omitted.
6. The system of claim 1 , wherein the omission of the restore operation is configured to reduce a charging time of the dynamic memory cell such that data stored in the dynamic memory cell is lost.
7. A memory for an artificial neural network (ANN), the memory comprising:
a memory controller; and
at least one dynamic memory cell electrically connected to a bit line and a word line, the at least one dynamic memory cell configured to perform a read-discard operation from the memory controller to selectively omit a restore operation during a read operation,
wherein the at least one dynamic memory cell includes a first area configured to store output feature map data of an ANN model corresponding to the read-discard operation based on an ANN data locality, and
wherein the memory controller is further configured to determine that the output feature map data is not reused during the read operation after the storing of the output feature map data.
8. The memory of claim 7 , wherein the at least one dynamic memory cell includes a first area configured to store data corresponding to the read-discard operation.
9. The memory of claim 7 , wherein data corresponding to the read-discard operation is a feature map data of an artificial neural network model.
10. The memory of claim 7 ,
wherein the at least one dynamic memory cell includes an area corresponding to the read-discard operation, and
wherein the area corresponding to the read-discard operation is set in a unit of the word line.
11. The memory of claim 7 , wherein a refresh operation of the word line corresponding to the read-discard operation is deactivated until a write operation.
12. A system for an artificial neural network (ANN), the system comprising:
at least one memory cell array of N columns and M rows;
a memory controller configured to operate at least a portion of a read operation as a read-discard operation based on sequential access information, when the at least one memory cell array receives a command for the read operation; and
a processor configured to provide ANN data locality information to the memory controller, wherein the at least one memory cell array receives a command for the read-discard operation by which stored data is read, and wherein the at least one memory cell array receives the read-discard operation command when the stored data is an output feature map and the stored data is read.
13. The system of claim 12 , wherein the sequential access information includes a repeating pattern of an input feature map, a kernel, and an output feature map in order.
14. The system of claim 12 , wherein the sequential access information includes a repeating pattern of a kernel, an input feature map, and an output feature map in order.
15. The system of claim 12 ,
wherein the memory controller includes a cache memory,
wherein the memory controller is further configured to store data of at least one subsequent processing step performed by a processor, and
wherein the at least one subsequent processing step is based on a current processing step and includes a request sent from the at least one memory cell array to the cache memory.
16. The system of claim 12 , wherein the sequential access information includes information on a predetermined operation sequence of an artificial neural network to be processed by a processor.