IP Library › Granted Patent US 11,888,046
Granted Patent B2
US 11,888,046 · App. 17/515,883 · Granted Jan 30, 2024

Epitaxial fin structures of finFET having an epitaxial buffer region and an epitaxial capping region

Inventors: Hsueh-Chang Sung (Zhubei, TW); Kun-Mu Li (Zhudong Township, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/66636H01L21/0262H01L21/02532H01L21/02576H01L21/02579H01L21/02609H01L21/3065H01L21/3085H01L29/045H01L29/0847H01L29/66545H01L29/66795H01L29/785H01L29/7848H01L29/7851H01L29/0653
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Quick Facts
Patent No.
US 11,888,046
App. No.
17/515,883
Granted
Jan 30, 2024
Kind
B2
Abstract

A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.

Claims (48)

1. A semiconductor device, comprising:

a substrate; and

a fin structure on the substrate, comprising:

a first epitaxial region and a second epitaxial region separated by a dielectric region;

a merged epitaxial region on the first epitaxial region and the second epitaxial region, wherein a top surface of the merged epitaxial region is substantially parallel to the substrate;

an epitaxial buffer region on the top surface of the merged epitaxial region, wherein a length of a horizontal interface between the epitaxial buffer region and the merged epitaxial region is greater than a horizontal length of the dielectric region; and

an epitaxial capping region on the epitaxial buffer region and side surfaces of the merged epitaxial region.

2. The semiconductor device of claim 1 , wherein the epitaxial buffer region is present on a (100) crystal plane and absent from a (111) crystal plane of the merged epitaxial region.

3. The semiconductor device of claim 1 , wherein the epitaxial capping region is on a (111) crystal plane of the merged epitaxial region.

4. The semiconductor device of claim 1 , wherein:

the first and second epitaxial regions comprise a first dopant concentration;

the merged epitaxial region comprises a second dopant concentration different from the first dopant concentration; and

the epitaxial buffer region comprises a third dopant concentration different from the first and second dopant concentrations.

5. The semiconductor device of claim 4 , wherein:

the first and second epitaxial regions comprise a first Ge atomic concentration;

the merged epitaxial region comprises a second Ge atomic concentration greater than the first Ge atomic concentration; and

the epitaxial buffer region comprises a third Ge atomic concentration smaller than the first and second Ge atomic concentrations.

6. The semiconductor device of claim 4 , further comprising:

a first pair of unmerged epitaxial regions, on the substrate, having the first dopant concentration; and

a second pair of unmerged epitaxial regions, on the first pair of unmerged epitaxial regions, having the second dopant concentration.

7. A semiconductor device, comprising:

a substrate;

a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure on the substrate;

a merged epitaxial region over the first and second fin structures;

a first unmerged epitaxial region and a second unmerged epitaxial region over the third and fourth fin structures, respectively;

an epitaxial buffer region over a top surface of the merged epitaxial region, wherein the top surface is substantially parallel to the substrate and having a length greater than a spacing between the first and second fin structures, and wherein a height of the merged epitaxial region is greater than heights of the first and second unmerged epitaxial regions;

a first epitaxial capping region over the epitaxial buffer region and side surfaces of the merged epitaxial region; and

a second epitaxial capping region directly over top and side surfaces of the first and second unmerged epitaxial region, respectively.

8. The semiconductor device of claim 7 , wherein the first epitaxial capping region is in direct contact with the side surfaces of the merged epitaxial region.

9. The semiconductor device of claim 8 , wherein the side surfaces of the merged epitaxial region comprises a (111) crystal plane.

10. The semiconductor device of claim 8 , wherein a portion of the side surfaces of the merged epitaxial region is substantially perpendicular to the substrate.

11. The semiconductor device of claim 7 , wherein the side surfaces of the first and second unmerged epitaxial regions substantially perpendicular to the substrate are formed by an etch back process to increase a distance between the first and second unmerged epitaxial regions.

12. The semiconductor device of claim 7 , wherein the epitaxial buffer region comprises from about 10 atomic percent to 15 atomic percent of germanium.

13. The semiconductor device of claim 7 , wherein the epitaxial buffer region is over top surfaces of the first and second fin structures.

14. A semiconductor device, comprising:

a substrate;

a first fin structure and a second fin structure on the substrate, wherein the first and second fin structures are separated by a first spacing;

a third fin structure and a fourth fin structure on the substrate, wherein the third and fourth fin structures are separated by a second spacing greater than the first spacing;

a merged epitaxial region over the first and second fin structures;

unmerged epitaxial regions over the third and fourth fin structures, respectively; and

an epitaxial buffer region over a top surface of the merged epitaxial region and not over top surfaces of the unmerged epitaxial regions, wherein a length of a horizontal interface between the epitaxial buffer region and the merged epitaxial region is greater than the first spacing, and wherein a height of the merged epitaxial region is greater than heights of the unmerged epitaxial regions.

15. The semiconductor device of claim 14 , wherein the merged epitaxial region is over a void structure that is between the first and second fin structures.

16. The semiconductor device of claim 14 , further comprising:

an epitaxial capping region in contact with a top surface of the epitaxial buffer region and side surfaces of the merged epitaxial region.

17. The semiconductor device of claim 14 , wherein the top surface of the merged epitaxial region comprises a (100) crystal plane.

18. The semiconductor device of claim 17 , wherein a first side surface, adjacent to the top surface, of the merged epitaxial region comprises a (111) crystal plane, and wherein a second side surface, adjacent to the first side surface, of the merged epitaxial region is substantially perpendicular to the substrate.

19. The semiconductor device of claim 14 , wherein the merged epitaxial region comprises from about 35 atomic percent to about 70 atomic percent of germanium.

20. The semiconductor device of claim 14 , wherein the merged epitaxial region is over top surfaces of the first and second fin structures.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 16, 2021
From: SUNG, HSUEH-CHANG; LI, KUN-MU
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 058121/0100 →
Continuity (4)
Continuation 16908057 · Jun 22, 2020
Division 15581778 · Apr 28, 2017
Provisional Application 62428220 · Nov 30, 2016
Related Publication 20220059676A1 · Feb 24, 2022
Cited By (1)
US 12,538,529