Multiplexing sample-and-hold circuit

1. A signal processing circuit, comprising:

a first sample and hold circuit; and

a second sample and hold circuit,

the first sample and hold circuit comprising:

a hold capacitor;

an input switch connected between a common input node and the hold capacitor;

a signal path amplifier having an input connected to the hold capacitor; and

an output switch connected between an output of the signal path amplifier and a common output node,

an input of a voltage feedback amplifier being connected to the hold capacitor, and

an output of the voltage feedback amplifier being operatively coupled to an internal node of the input switch,

wherein the input switch comprises:

a first series switch;

a second series switch; and

a voltage feedback switch,

the first series switch being connected between the common input node and the internal node,

the second series switch being connected between the internal node and the hold capacitor, and

the voltage feedback switch being connected between the output of the voltage feedback amplifier and the internal node, and

a clock circuit having an input, a first output and a second output, the clock circuit being configured to receive a reference clock signal and to produce:

at the first output, a first clock signal having the same frequency as the reference clock signal,

at the second output, a second clock signal having the same frequency as the reference clock signal,

the first output being operatively coupled to one or more control terminals of the first series switch and of the second series switch, and

the second output being operatively coupled to the voltage feedback switch.

2. The signal processing circuit of claim 1 , wherein the voltage feedback amplifier is the signal path amplifier.

3. The signal processing circuit of claim 1 , wherein the voltage feedback amplifier is a switch feedback amplifier, separate from the signal path amplifier.

4. The signal processing circuit of claim 1 , wherein the operative coupling of the voltage feedback amplifier and the internal node of the input switch is configured to increase the effective resistance of the input switch by a factor of at least 100.

5. The signal processing circuit of claim 1 , wherein the effective resistance of the input switch is greater than 100,000 ohms.

6. The signal processing circuit of claim 1 , wherein the first series switch comprises a first transistor connected in parallel with a second transistor.

7. The signal processing circuit of claim 6 , wherein the first transistor is an n-channel field effect transistor, and the second transistor is a p-channel field effect transistor.

8. The signal processing circuit of claim 6 , wherein the second series switch comprises an n-channel field effect transistor connected in parallel with a p-channel field effect transistor.

9. The signal processing circuit of claim 1 , wherein the clock circuit is configured to cause, in order:

the first series switch and the second series switch to open;

the voltage feedback switch to close;

the voltage feedback switch to open; and

the first series switch and the second series switch to close.

10. The signal processing circuit of claim 1 , wherein:

the first series switch comprises a first field effect transistor connected in parallel with a second field effect transistor;

the second series switch comprises a first field effect transistor connected in parallel with a second field effect transistor; and

the first output of the clock circuit is connected:

through a first inverter and a second inverter, connected in cascade, to:

the gate of the first field effect transistor of the first series switch, and

the gate of the first field effect transistor of the second series switch; and

through a third inverter to:

the gate of the second field effect transistor of the first series switch, and

the gate of the second field effect transistor of the second series switch.

11. The signal processing circuit of claim 10 , wherein each of the second inverter and the third inverter is connected to a respective bandwidth-limiting circuit.

12. The signal processing circuit of claim 11 , wherein each of the bandwidth-limiting circuits limits the bandwidth of a corresponding inverter to a respective bandwidth, each of the respective bandwidths being less than 10 GHz or less than a frequency of a system clock signal.

13. The signal processing circuit of claim 12 , wherein:

the voltage feedback switch comprises a first field effect transistor connected in parallel with a second field effect transistor; and

the second output of the clock circuit is connected:

to the gate of the first field effect transistor of the voltage feedback switch, and

through one inverter, to the gate of the second field effect transistor of the voltage feedback switch.

14. The signal processing circuit of claim 1 , wherein:

the second sample and hold circuit comprises:

a hold capacitor,

an input switch connected between the common input node and the hold capacitor of the second sample and hold circuit,

a signal path amplifier having an input connected to the hold capacitor of the second sample and hold circuit,

an output switch connected between an output of the signal path amplifier of the second sample and hold circuit and the common output node; and

the output of the signal path amplifier of the second sample and hold circuit is operatively coupled to an internal node of the input switch of the second sample and hold circuit.

15. The signal processing circuit of claim 1 , wherein the signal path amplifier comprises a source follower amplifier.

16. The signal processing circuit of claim 1 , wherein the signal path amplifier comprises a differential amplifier.

17. The signal processing circuit of claim 1 , further comprising an output stage, having an input connected to the common output node.

18. The signal processing circuit of claim 17 , wherein the output stage comprises a source follower amplifier.

19. The signal processing circuit of claim 17 , wherein the output stage comprises a differential amplifier.