IP Library › Granted Patent US 11,870,889
Granted Patent B2
US 11,870,889 · App. 17/516,924 · Granted Jan 9, 2024

Method and apparatus with homomorphic encryption

Inventors: Jong-Seon No (Seoul, KR); Yongwoo Lee (Seoul, KR); Young-Sik Kim (Gwangju, KR)
Assignees: Samsung Electronics Co., Ltd.; Seoul National University R & DB Foundation; Industry Academic Cooperation Foundation, Chosun University
H04L9/0825G06F7/523G06F7/766G06F17/16H04L9/008H04L9/0618
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Quick Facts
Patent No.
US 11,870,889
App. No.
17/516,924
Granted
Jan 9, 2024
Kind
B2
Abstract

A processor-implemented method with homomorphic encryption includes: receiving a first ciphertext corresponding to a first modulus; generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation.

Claims (44)

1. A processor-implemented method with homomorphic encryption, the method comprising:

receiving a first ciphertext corresponding to a first modulus;

generating a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext; and

performing bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation,

wherein the performing of the bootstrapping comprises:

performing a permutation operation on the second ciphertext; and

performing the bootstrapping by performing a key switching operation based on a result of the permutation operation, and

wherein the performing of the bootstrapping by performing the key switching operation based on the result of the permutation operation comprises:

performing a rescaling operation based on the permutation operation;

performing a decompose operation on a result of the rescaling operation; and

performing a sum of multiplications on a result of the decompose operation.

2. The method of claim 1 , wherein the generating of the second ciphertext comprises generating the second ciphertext by performing modulus raising on the first ciphertext such that the value of the first modulus multiplied by a predetermined value is the second modulus.

3. The method of claim 1 , wherein the performing of the rescaling operation based on the permutation operation comprises:

performing a multiplication of the result of the permutation operation and a plaintext; and

rescaling a result of the multiplication.

4. The method of claim 3 , wherein the performing of the multiplication between the result of the permutation operation and the plaintext comprises performing a multiplication of the result of the permutation operation and a diagonal component of a matrix corresponding to the plaintext.

5. The method of claim 1 , wherein the performing of the bootstrapping by performing the key switching operation based on the result of the permutation operation further comprises:

generating an addition result by adding a result of the sum of multiplications; and

performing a modulus down operation on the addition result.

6. The method of claim 1 , wherein the performing of the bootstrapping comprises performing the bootstrapping by performing modulus reduction on a result of encoding the second ciphertext.

7. The method of claim 6 , wherein the performing of the bootstrapping by performing the modulus reduction on the result of encoding the second ciphertext comprises performing the bootstrapping by decoding a result of the modulus reduction.

8. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, configure the processor to perform the method of claim 1 .

9. An apparatus with homomorphic encryption, the apparatus comprising:

a receiver configured to receive a first ciphertext corresponding to a first modulus; and

a processor configured to

generate a second ciphertext corresponding to a second modulus by performing modulus raising on the first ciphertext, and

perform bootstrapping by encoding the second ciphertext using a commutative property and an associative property of operations included in a rotation operation,

wherein, for the performing of the bootstrapping, the processor is configured to:

perform a permutation operation on the second ciphertext; and

perform the bootstrapping by performing a key switching operation based on a result of the permutation operation, and

wherein, for the performing of the bootstrapping by performing the key switching operation based on the result of the permutation operation, the processor is configured to:

perform a rescaling operation based on the permutation operation;

perform a decompose operation on a result of the rescaling operation; and

perform a sum of multiplications on a result of the decompose operation.

10. The apparatus of claim 9 , wherein, for the generating of the second ciphertext, the processor is configured to generate the second ciphertext by performing modulus raising on the first ciphertext such that the value of the first modulus multiplied by a predetermined value is the second modulus.

11. The apparatus of claim 9 , wherein, for the performing of the rescaling operation based on the permutation operation, the processor is configured to:

perform a multiplication of the result of the permutation operation and a plaintext; and

rescale a result of the multiplication.

12. The apparatus of claim 11 , wherein, for the performing of the multiplication between the result of the permutation operation and the plaintext, the processor is configured to perform a multiplication of the result of the permutation operation and a diagonal component of a matrix corresponding to the plaintext.

13. The apparatus of claim 9 , wherein, for the performing of the bootstrapping by performing the key switching operation based on the result of the permutation operation, the processor is configured to:

generate an addition result by adding a result of the sum of multiplications; and

perform a modulus down operation on the addition result.

14. The apparatus of claim 9 , wherein, for the performing of the bootstrapping, the processor is configured to perform the bootstrapping by performing modulus reduction on a result of encoding the second ciphertext.

15. The apparatus of claim 14 , wherein, for the performing of the bootstrapping by performing the modulus reduction on the result of encoding the second ciphertext, the processor is further configured to perform the bootstrapping by decoding a result of the modulus reduction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2021
From: NO, JONG-SEON; LEE, YONGWOO; KIM, YOUNG-SIK
To: SAMSUNG ELECTRONICS CO., LTD.; SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION; INDUSTRY ACADEMIC COOPERATION FOUNDATION, CHOSUN UNIVERSITY
Reel/Frame 057993/0413 →
Priority Claims (2)
KR 10-2021-0024262 · Feb 23, 2021 · national
KR 10-2021-0062640 · May 14, 2021 · national
Continuity (1)
Related Publication 20220271922A1 · Aug 25, 2022