IP Library Granted Patent US 12,635,510
Granted Patent B2
US 12,635,510 · App. 17/517,247 · Granted May 19, 2026

Interconnect structures and methods for forming same

Inventors: Cyprian Emeka Uzoh (San Jose, CA); Laura Wills Mirkarimi (Sunol, CA)
Assignee: Adeia Semiconductor Technologies LLC
H10W20/46H10W20/033H10W20/048H10W20/072H10W20/42H10W20/425H10W20/4424H10W20/48H10W70/093H10W70/60H10W72/019H10W72/90H10W72/352H10W80/016H10W80/102H10W80/312H10W80/327H10W90/722H10W90/732H10W90/734H10W90/792H10W90/794
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Quick Facts
Patent No.
US 12,635,510
App. No.
17/517,247
Granted
May 19, 2026
Kind
B2
Abstract

A method for forming an interconnect structure in an element is disclosed. The method can include patterning a cavity in a non-conductive material. The method can include exposing a surface of the cavity in the non-conductive material to a surface nitriding treatment. The method can include depositing a conductive material directly onto the treated surface after the exposing.

Claims (47)

1 . An element comprising an interconnect structure, the interconnect structure comprising:

a non-conductive semiconductor material comprising a primary region and an interface region;

a conductive material provided directly over the non-conductive semiconductor material with the interface region between the conductive material and the primary region;

wherein of the non-conductive semiconductor material only the non-conductive semiconductor material of the interface region is nitridized; and

wherein an amount of nitrogen varies through a depth of the interface region between the primary region and the conductive material.

2 . The element of claim 1 , wherein the non-conductive semiconductor material comprises a silicon based material.

3 . The element of claim 2 , wherein the conductive material comprises copper.

4 . The element of claim 2 , wherein the interface region comprises silicon and nitrogen.

5 . The element of claim 1 , wherein the amount of nitrogen is maximized at a boundary with the conductive material.

6 . The element of claim 1 , wherein the non-conductive semiconductor material is patterned with one or more sidewalls that define one or more cavities, the interface region disposed along the sidewalls of the one or more cavities.

7 . The element of claim 1 , wherein no barrier layer is disposed between the non-conductive semiconductor material and the conductive material.

8 . The element of claim 1 , wherein a width of the interface region is less than 10 nm.

9 . The element of claim 8 , wherein the width of the interface region is less than 5 nm.

10 . A method for forming an interconnect structure in an element, the method comprising:

forming one or more cavities by patterning a non-conductive semiconductor material;

exposing one or more surfaces of the patterned non-conductive semiconductor material to a plasma comprising a surface-treating species;

forming a conductive material at least partially filling the treated surfaces of the patterned non-conductive semiconductor material; and

forming a planar surface by removing portions of the conductive and non-conductive semiconductor materials.

11 . The method of claim 10 , comprising exposing the one or more surfaces of the patterned non-conductive semiconductor material to a nitrogen-containing plasma.

12 . The method of claim 10 , comprising forming the conductive material over the treated surfaces without an intervening conductive barrier layer between the conductive material and the non-conductive semiconductor material.

13 . The method of claim 10 , wherein the conductive material has a resistivity in a range of 1.5 micro ohm-cm to 50 micro ohm-cm.

14 . The method of claim 10 , wherein the conductive material fills at least 50% of depth of the one or more cavities.

15 . A method for forming an interconnect structure in an element, the method comprising:

providing a non-conductive semiconductor material having a cavity;

exposing a surface of the cavity in the non-conductive semiconductor material to a surface nitriding treatment;

depositing a conductive material onto the treated surface after the exposing;

planarizing the conductive material to remove unwanted materials including portions of the non-conductive semiconductor material;

providing a protective layer over the planarized conductive material and non-conductive semiconductor material; and

removing a portion of the protective layer that is disposed over the planarized conductive material.

16 . The method of claim 15 , wherein:

the surface nitriding treatment is a first surface nitriding treatment, and

the method further comprises:

providing a second non-conductive semiconductor material over the non-conductive semiconductor material and the conductive material;

patterning a second cavity in the second non-conductive semiconductor material;

exposing a second surface of the second cavity in the second non-conductive semiconductor material to a second surface nitriding treatment; and

depositing a second conductive material onto the second treated surface after the exposing the second surface.

17 . The method of claim 16 , further comprising:

exposing an upper surface of the non-conductive semiconductor material to an intervening nitriding treatment before providing the second non-conductive semiconductor material; and

providing the second non-conductive semiconductor material on the treated upper surface.

18 . The method of claim 15 , further comprising patterning the non-conductive semiconductor material prior to exposure to the surface nitriding treatment.

19 . The method of claim 15 , wherein the non-conductive semiconductor material comprises a silicon based material.

20 . The method of claim 15 , further comprising, before exposing the surface to the surface nitriding treatment, treating the surface with one or more of carbon (C), boron (B), cobalt (Co), and manganese (Mn).

21 . An element comprising an interconnect structure, the interconnect structure comprising:

a semiconductor material comprising a primary region and an interface region, wherein the semiconductor material is silicon;

a conductive material provided directly over the semiconductor material with the interface region between the conductive material and the primary region;

wherein of the semiconductor material only the semiconductor material of the interface region is nitridized; and

wherein an amount of nitrogen varies through a depth of the interface region between the primary region and the conductive material.

Assignments (4)
CHANGE OF NAME Recorded Jan 9, 2024
From: INVENSAS LLC
To: ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
Reel/Frame 066238/0778 →
SECURITY INTEREST Recorded May 19, 2023
From: ADEIA GUIDES INC.; ADEIA MEDIA HOLDINGS LLC; ADEIA MEDIA SOLUTIONS INC.; ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.; ADEIA SEMICONDUCTOR SOLUTIONS LLC; ADEIA SEMICONDUCTOR TECHNOLOGIES LLC
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 063707/0884 →
CERTIFICATE OF CONVERSION & CHANGE OF NAME Recorded Apr 4, 2022
From: INVENSAS CORPORATION
To: INVENSAS LLC
Reel/Frame 059581/0435 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2022
From: UZOH, CYPRIAN EMEKA; MIRKARIMI, LAURA WILLS
To: INVENSAS CORPORATION
Reel/Frame 059151/0633 →