IP Library Granted Patent US 12,469,199
Granted Patent B2
US 12,469,199 · App. 17/518,229 · Granted Nov 11, 2025

Programmable GPU command buffers using mutable command lists

Inventors: Jaroslaw Chodor (Bydgoszcz, PL); Zbigniew Zdanowicz (Gdansk PM, PL)
Assignee: Intel Corporation
G06T15/005G06F8/41G06F9/3005G06F9/323G06F9/45516G06F9/4843G06F9/545G06T1/20G06T1/60
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,469,199
App. No.
17/518,229
Granted
Nov 11, 2025
Kind
B2
Abstract

Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and/or an executable jump command.

Claims (53)

1 . A computing system, comprising:

a first processor; and

a memory coupled to the first processor to store instructions which, when executed by the first processor, cause the first processor to:

compile a source file to generate a command list, wherein the command list comprises a set of hardware-specific executable commands for a second processor comprising a graphics processing unit (GPU); and

dispatch the command list to a command buffer for execution by the GPU, the command list compiled by the first processor to be reconfigurable at runtime by the GPU, wherein reconfiguration of the command list comprises change a flow order of the command list.

2 . The computing system of claim 1 , wherein the first processor is to dispatch the command list via an application programming interface (API) call to a graphics driver, wherein the API call is to bypass generating GPU commands for the command list, and wherein the graphics driver is to bypass encoding the set of hardware-specific executable commands in the command list.

3 . The computing system of claim 1 , wherein the instructions, when executed, further cause the first processor to:

store the command list; and

retrieve the command list from storage prior to dispatching the command list to the command buffer.

4 . The computing system of claim 1 , wherein the instructions, when executed, further cause the first processor to:

compile a subset source file to generate a subset command list;

store the subset command list;

retrieve the subset command list from storage; and

add the subset command list to the command list prior to dispatching the command list to the command buffer;

wherein the subset source file includes a function specific to a particular shader or kernel.

5 . The computing system of claim 1 , wherein the source file includes function calls specific to GPU hardware blocks, and wherein the command list includes executable commands directed to the GPU hardware blocks based on the function calls.

6 . The computing system of claim 1 , wherein the command list includes one or more of an executable loop command, an executable conditional branch command, or an executable jump command.

7 . The computing system of claim 1 , wherein the command list comprises a first command list for dispatching to a first command buffer for execution by the GPU and a second command list for dispatching to a second command buffer for execution by the GPU, and wherein the first command list includes an instruction to wait for execution until a coordinating event is produced by the second command list.

8 . At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to:

compile, by a first processor, a source file to generate a command list, wherein the command list comprises a set of hardware-specific executable commands for a second processor comprising a graphics processing unit (GPU); and

dispatch the command list to a command buffer for execution by the GPU, the command list compiled by the first processor to be reconfigurable at runtime by the GPU, wherein reconfiguration of the command list comprises change a flow order of the command list.

9 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the first processor is to dispatch the command list via an application programming interface (API) call to a graphics driver, wherein the API call is to bypass generating GPU commands for the command list, and wherein the graphics driver is to bypass encoding the set of hardware-specific executable commands in the command list.

10 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the set of instructions, when executed, further cause the computing system to:

store the command list; and

retrieve the command list from storage prior to dispatching the command list to the command buffer.

11 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the set of instructions, when executed, further cause the computing system to:

compile a subset source file to generate a subset command list;

store the subset command list;

retrieve the subset command list from storage; and

add the subset command list to the command list prior to dispatching the command list to the command buffer;

wherein the subset source file includes a function specific to a particular shader or kernel.

12 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the source file includes function calls specific to GPU hardware blocks, and wherein the command list includes executable commands directed to the GPU hardware blocks based on the function calls.

13 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the command list includes one or more of an executable loop command, an executable conditional branch command, or an executable jump command.

14 . The at least one non-transitory computer readable storage medium of claim 8 , wherein the command list comprises a first command list for dispatching to a first command buffer for execution by the GPU and a second command list for dispatching to a second command buffer for execution by the GPU, and wherein the first command list includes an instruction to wait for execution until a coordinating event is produced by the second command list.

15 . A method comprising:

compiling, by a first processor, a source file to generate a command list, wherein the command list comprises a set of hardware-specific executable commands for a second processor comprising a graphics processing unit (GPU); and

dispatching the command list to a command buffer for execution by the GPU, the command list compiled by the first processor to be reconfigurable at runtime by the GPU, wherein reconfiguration of the command list comprises change a flow order of the command list.

16 . The method of claim 15 , wherein the first processor dispatches the command list via an application programming interface (API) call to a graphics driver, wherein the API call bypasses generating GPU commands for the command list, and wherein the graphics driver bypasses encoding the set of hardware-specific executable commands in the command list.

17 . The method of claim 15 , further comprising:

storing the command list; and

retrieving the command list from storage prior to dispatching the command list to the command buffer.

18 . The method of claim 15 , further comprising:

compiling a subset source file to generate a subset command list;

storing the subset command list;

retrieving the subset command list from storage; and

adding the subset command list to the command list prior to dispatching the command list to the command buffer;

wherein the subset source file includes a function specific to a particular shader or kernel.

19 . The method of claim 15 , wherein the source file includes function calls specific to GPU hardware blocks, and wherein the command list includes executable commands directed to the GPU hardware blocks based on the function calls.

20 . The method of claim 15 , wherein the command list includes one or more of an executable loop command, an executable conditional branch command, or an executable jump command.

21 . The method of claim 15 , wherein the command list comprises a first command list for dispatching to a first command buffer for execution by the GPU and a second command list for dispatching to a second command buffer for execution by the GPU, and wherein the first command list includes an instruction to wait for execution until a coordinating event is produced by the second command list.

22 . An apparatus comprising:

first logic of a first processor to compile a source file to generate a command list, wherein the command list comprises a set of hardware-specific executable commands for a second processor comprising a graphics processing unit (GPU); and

second logic of the first processor to dispatch the command list to a command buffer for execution by the GPU, the command list compiled by the first processor to be reconfigurable at runtime by the GPU, wherein reconfiguration of the command list comprises change a flow order of the command list.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2022
From: CHODOR, JAROSLAW; ZDANOWICZ, ZBIGNIEW
To: INTEL CORPORATION
Reel/Frame 058654/0832 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2022
From: CHODOR, JAROSLAW; ZDANOWICZ, ZBIGNIEW
To: INTEL CORPORATION
Reel/Frame 058633/0629 →
Continuity (1)
Related Publication 20230138635A1 · May 4, 2023
References Cited (13)
US 5974571A · Riesenman · 1999 [cited by examiner]
US 9892482B2 · You · 2018 [cited by examiner]
US 10437637B1 · Koneru et al. · 2019 [cited by applicant]
US 11354267B1 · Shah · 2022 [cited by examiner]
US 20150221059A1 · Baker · 2015 [cited by examiner]
US 20170061569A1 · Sathe · 2017 [cited by examiner]
US 20180307487A1 · Maiyuran · 2018 [cited by examiner]
US 20200174707A1 · Johnson · 2020 [cited by examiner]
H. Lee et al., “A Gpu Kernel Transactionization Scheme for Preemptive Priority Scheduling,” 2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Porto, Portugal, 2018, 11 pages. [cited by applicant]
Extended European Search Report in Application No. 22198988.2 mailed Mar. 3, 2023. [cited by applicant]
M. Mrozek et al., “GPU Daemon—Road to Zero Cost Submission”, Apr. 19, 2016, 4 pages. [cited by applicant]
M. Mrozek et al. “GPU Daemon—Road to Zero Cost Submission”, PowerPoint Presentation, 2016, 28 pages. [cited by applicant]
Khronos Group, “The OpenCL Specification”, Jul. 21, 2015, 288 pages. [cited by applicant]