Compiler optimization to reduce the control flow divergence

1. A graphics processing system comprising:

a graphics processor execution logic and shared memory;

a shader compiler unit to compile a shader program for execution by a single instruction multiple data (SIMD) logic of the execution logic of the graphic processor, the shader compiler further to optimize the shader program during the compile, wherein to optimize the shader program at compile time includes to determine if any unstructured control flow having multiple entries or exits exists within the shader program and to convert any unstructured control flow including a divergent control flow block of parallel instructions into a divergent control flow block and a non-divergent control flow block of instructions to enhance utilization of the SIMD logic of the execution logic, wherein the shader compiler is to further optimize by parallelizing along different axis of parallelism for each block of the control flow to indicate that divergent code flows are executed serially in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.

2. The system as in claim 1 , wherein the shader program is a single program multiple data (SPMD) shader program and the shader compiler unit is to configure the non-divergent block of instructions to be performed by single instruction multiple data (SIMD) logic of the execution logic in the graphics processor.

3. The system as in claim 1 , wherein the shader compiler unit is to configure the divergent block of instructions to identify inputs to each block of control flow.

4. The system as in claim 3 , wherein the shader compiler unit is to further to configure the non-divergent block of instructions to allocate a buffer to store the inputs for threads in a thread group and append inputs for the threads to the buffer.

5. The system as in claim 4 , wherein the instructions of the shader program are to allocate the buffer to store the inputs for the threads in shared memory of the graphics processor.

6. The system as in claim 4 , wherein the shader compiler unit is to further to convert instructions of the shader program to atomically increment a separate counter for each input for the block of the control flow.

7. The system as in claim 6 , wherein the shader compiler unit is to further to allocate the counters for each input in shared memory of the graphics processor.

8. The system as in claim 6 , wherein the shader compiler unit is to configure the thread groups to synchronize after executing a block of instructions having a divergent control flow.

9. The system as in claim 6 , wherein the shader compiler is to configure instructions of the shader program to parallelize each axis of parallelism within a non-divergent block of instructions using the buffer having the inputs for the threads in the thread group and the atomically incremented counter.

10. A computer-implemented method at a graphics processing system, the method comprising:

identifying inputs for instructions in each block of control flow for a shader program;

allocating a buffer to store inputs for threads in a thread group of the shader program;

convert instructions for each block of the control flow to atomically increment a counter for each input of the block;

synchronize the shader thread groups associated with each block; and

parallelize along different axis of parallelism for each block of the control flow to indicate that divergent code flows are executed in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.

11. The method as in claim 10 , further comprising allocating the buffer to store the inputs for the threads in shared memory of a graphics processor in the graphics processing system.

12. The method as in claim 10 , further comprising allocating the counter to count the inputs for the threads in shared memory of a graphics processor in the graphics processing system.

13. The method as in claim 10 , further comprising analyzing the shader program for structured control flows.

14. The method as in claim 13 , further comprising determining whether the shader program includes an unstructured control flow having multiple entries or exits and converting the unstructured control flow to a structured control flow having a single entry and a single exit.

15. A non-transitory computer-readable storage medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising:

identifying inputs for instructions in each block of control flow for a shader program;

allocating a buffer to store inputs for threads in a thread group of the shader program;

convert instructions for each block of the control flow to atomically increment a counter for each input of the block;

synchronize the shader thread groups associated with each block; and

for each block of the control flow, parallelize along a different axis of parallelism to indicate that divergent code flows are executed in parallel by single instruction multiple data (SIMD) logic such that no divergence occurs within each block of the control flow, wherein divergence for the control flow is defined as including multiple, mutually exclusive control flow paths.

16. The medium as in claim 15 , further comprising instructions to perform operations including allocating the buffer to store the inputs for the threads in shared memory of a graphics processor.

17. The medium as in claim 15 , further comprising instructions to perform operations including allocating the counter to count the inputs for the threads in shared memory of a graphics processor.

18. The medium as in claim 15 , further comprising instructions to perform operations including analyzing the shader program for structured control flows.

19. The medium as in claim 18 , further comprising instructions to perform operations including determining whether the shader program includes an unstructured control flow having multiple entries or exits and converting the unstructured control flow to a structured control flow having a single entry and a single exit.

20. The medium as in claim 15 , further comprising instructions to perform operations including determining if sufficient free shared memory exists to allocate a counter for each block of the control flow and bypassing optimization of the shader program based on the determination.