Gate-all-around field effect transistor with bottom dielectric isolation
A semiconductor device includes a semiconductor substrate, a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the semiconductor substrate, a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate, a first S/D (source/drain region disposed in the first gate canyon, a second S/D region disposed in the second gate canyon, a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness, and a second BDI element disposed below the second S/D region and having a second BDI thickness. The first BDI thickness exceeds the second BDI thickness.
1. A semiconductor device comprising:
a semiconductor substrate;
a first pair of FET (field effect transistor) gate structures separated by a first gate canyon having a first gate canyon spacing, disposed upon the substrate;
a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing, disposed upon the substrate;
a first S/D (source/drain) region disposed in the first gate canyon;
a second S/D region disposed in the second gate canyon;
a first BDI (bottom dielectric isolation) element disposed below the first S/D region and having a first BDI thickness; and
a second BDI element disposed below the second S/D region and having a second BDI thickness;
wherein the first BDI thickness exceeds the second BDI thickness.
2. The semiconductor device according to claim 1 , further comprising a first continuous BDI element below the first pair of FET gate structures and including the first BDI element.
3. The semiconductor device according to claim 2 , wherein the first S/D region extends below an upper surface of the first continuous BDI element.
4. The semiconductor device according to claim 1 , further comprising a second continuous BDI element below the second pair of FET gate structures and including the second BDI element.
5. The semiconductor device according to claim 4 , wherein the second S/D region extends below an upper surface of the second continuous BDI element.
6. The semiconductor device according to claim 1 , wherein the first gate canyon spacing exceeds the second gate canyon spacing.
7. The semiconductor device according to claim 1 , wherein the first S/D region extends below an upper surface of the semiconductor substrate.
8. A semiconductor device comprising:
a semiconductor substrate;
a first pair of FET (field effect transistor) gate structures separated by a first gate canyon and having a first gate canyon spacing disposed upon the semiconductor substrate;
a first S/D (source/drain region) disposed in the first gate canyon; and
a first BDI (bottom dielectric isolation) element disposed below the first pair of FET gate structures and the first S/D region;
wherein the first BDI element comprises a first thickness below the first pair of FET gate structures and a second thickness below the first S/D region;
wherein the first BDI element extends into the semiconductor substrate; and
wherein the first S/D region extends below an upper surface of the first BDI element.
9. The semiconductor device according to claim 8 , further comprising:
a second pair of FET gate structures separated by a second gate canyon having a second gate canyon spacing;
a second S/D region disposed in the second gate canyon; and
a second BDI element disposed below the second pair of FET gate structures and the second S/D region.
10. The semiconductor device according to claim 9 , wherein the second S/D region extends below an upper surface of the second BDI element.
11. The semiconductor device according to claim 9 , further comprising a second continuous BDI element below the second pair of FET gate structures and including the second BDI element.
12. The semiconductor device according to claim 9 , wherein the first gate canyon spacing exceeds the second gate canyon spacing.
13. The semiconductor device according to claim 9 , wherein the second BDI element extends into the semiconductor substrate.
14. A method of fabricating a semiconductor device, the method comprising:
forming a nanosheet layer stack including a bottom sacrificial nanosheet layer;
forming fins from the nanosheet stack;
forming dummy gates upon the fins;
recessing the fins between otherwise adjacent dummy gates;
removing the bottom sacrificial nanosheet layer;
forming a bottom dielectric isolation layer below the nanosheet stack;
recessing the bottom dielectric isolation layer between otherwise adjacent dummy gates; and
forming source/drain regions adjacent to the bottom dielectric layer and the otherwise adjacent dummy gates.
15. The method of fabricating a semiconductor device according to claim 14 , further comprising forming inner spacers between otherwise adjacent nanosheets.
16. The method of fabricating a semiconductor device according to claim 14 , further comprising forming gate sidewall spacers adjacent to the dummy gate.
17. The method of fabricating a semiconductor device according to claim 14 , wherein the bottom dielectric isolation layer comprises a flowable dielectric material.
18. The method of fabricating a semiconductor device according to claim 14 , wherein at least one source/drain region extends below an upper surface of the bottom dielectric layer.
19. The method of fabricating a semiconductor device according to claim 14 , wherein the bottom dielectric isolation layer comprises a continuous layer beneath the nanosheet stack and the source/drain regions.