IP Library Granted Patent US 12,340,273
Granted Patent B2
US 12,340,273 · App. 17/519,320 · Granted Jun 24, 2025

Quantum processor unit architecture for quantum computing via an arbitrarily programmable interaction connectivity graph

Inventors: Irfan Siddiqi (Berkeley, CA); Jie Luo (Berkeley, CA); Brian Marinelli (Berkeley, CA)
Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
G06N10/40G01R33/0358
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Quick Facts
Patent No.
US 12,340,273
App. No.
17/519,320
Granted
Jun 24, 2025
Kind
B2
Abstract

A superconducting quantum processor unit for quantum computing is provided. The processor unit is formed from the union of a qubit chip and a wiring chip with superconducting bonding bumps and spacers. The bumps may be densely distributed around active elements between the two chips and effectively form a Faraday-Cage around the qubits, control signal waveguides etc. The qubit chip has strategically spaced qubits and an inductively coupled probe line and the wiring chip has a bus coupling resonator with a number of voltage nodes and anti-nodes, a resonator pump and at least one SQUID. Magnetic flux applied through the SQUIDs changes their impedances and modifies the microwave boundary conditions of the bus. This allows in-situ shifting of electric field distributions of the resonance modes of the bus along the length of the bus. This tunes the coupling rates of the bus to all qubits simultaneously.

Claims (80)

1. A superconducting quantum processor unit apparatus for quantum computing, the apparatus comprising:

(a) a qubit chip, comprising:

(i) a planar substrate with a plurality of qubit chip surface bonding elements;

(ii) a plurality of qubits; and

(iii) a probe line inductively coupled to the qubits;

(b) a wiring chip, comprising:

(i) a planar substrate with a plurality of wiring chip surface bonding elements;

(ii) a bus coupling resonator with a plurality of voltage nodes and anti-nodes;

(iii) at least one Superconducting-Quantum-Interference-Device (SQUID) joined to the bus coupling resonator; and

(iv) a resonator pump connected to said bus coupling resonator through pump capacitors at said voltage anti-nodes;

(c) wherein said qubit chip is mounted to said wiring chip with the surface bonding elements of each chip to produce a superconducting quantum processor unit.

2. The apparatus of claim 1 , wherein each of said qubits comprise:

a transmon; and

a meandering readout resonator with a readout capacitor engaged with the transmon at one end and coupled to the probe line at the other with an inductive coupling;

wherein said readout resonator is configured to produce a set resonator frequency.

3. The apparatus of claim 2 , wherein each transmon comprises:

a qubit pad with a qubit ground capacitor;

a bus coupling capacitor;

a qubit XY control; and

a qubit Z control.

4. The apparatus of claim 1 , said probe line further comprising:

a Purcell filter; and

a parallel capacitor.

5. The apparatus of claim 1 , wherein said resonator pump further comprises waveguides positioned between each pump coupling capacitor creating a phase delay.

6. The apparatus of claim 1 , wherein said bonding elements of said qubit chip and said wiring chip comprise superconducting indium metal pillars distributed around the planar substrate for crosstalk suppression.

7. The apparatus of claim 6 , wherein said bonding elements of said qubit chip and said wiring chip further comprise a plurality of low-loss superconducting/dielectric hard spacers.

8. A superconducting quantum processor unit apparatus for quantum computing, the apparatus comprising:

(a) a wiring chip, comprising:

(i) a planar substrate with a plurality of wiring chip surface bonding elements;

(ii) a bus coupling resonator with a first row of a plurality of voltage nodes and anti-nodes coupled to a second row of a plurality of voltage nodes and anti-nodes parallel to the first row and separated by a gap;

(iii) a resonator pump disposed in said gap between said rows of voltage nodes, said resonator pump connected to each row of said bus coupling resonator through pump capacitors at said voltage anti-nodes of said first and second rows of nodes of the bus coupling resonator; and

(iv) a first Superconducting-Quantum-Interference-Device (SQUID) joined to the first row of voltage nodes and anti-nodes of the bus coupling resonator; and

(v) a second Superconducting-Quantum-Interference-Device (SQUID) joined to the second row of voltage nodes and anti-nodes of the bus coupling resonator;

(b) a qubit chip, comprising:

(i) a planar substrate with a plurality of qubit chip surface bonding elements with a distribution corresponding to said bonding elements of said wiring chip;

(ii) a first row of a plurality of qubits inductively coupled to a first probe line; and

(iii) a second row of a plurality of qubits inductively coupled to a second probe line;

(c) wherein said qubit chip is mounted to said wiring chip with the surface bonding elements to produce a superconducting quantum processor unit.

9. The apparatus of claim 8 , said first probe line and said second probe line further comprising:

a Purcell filter; and

a parallel capacitor.

10. The apparatus of claim 8 , wherein each of said qubits comprises:

a transmon; and

a meandering readout resonator with a readout capacitor engaged with the transmon at one end and coupled to the first or second probe line at the other with an inductive coupling;

wherein said readout resonator is configured to produce a set resonator frequency.

11. The apparatus of claim 10 , wherein said set resonator frequency of said qubits in said first and second rows of qubits incrementally increases from one end of a row to the other.

12. The apparatus of claim 10 , wherein each transmon comprises:

a qubit pad with a qubit ground capacitor;

a bus coupling capacitor;

a qubit XY control; and

a qubit Z control.

13. The apparatus of claim 8 , wherein said resonator pump further comprises waveguides positioned between pump capacitors creating a phase delay; and

wherein voltage phases of resonant anti-nodes are aligned with a travelling wave injected into the bus drive line resonator pump.

14. The apparatus of claim 8 , wherein said bonding elements of said qubit chip and said wiring chip comprise superconducting indium metal pillars distributed around the planar substrate for crosstalk suppression.

15. The apparatus of claim 14 , wherein said bonding elements of said qubit chip and said wiring chip further comprise a plurality of low-loss superconducting/dielectric hard spacers.

16. A superconducting quantum processor unit apparatus for quantum computing, the apparatus comprising:

(a) a wiring chip, comprising:

(i) a planar substrate with a plurality of wiring chip surface bonding elements;

(ii) a bus coupling resonator with a first row of four voltage nodes and anti-nodes coupled to a second row of four voltage nodes and anti-nodes parallel to the first row and separated by a gap, said anti-nodes facing the gap;

(iii) a resonator pump disposed in said gap between said rows of voltage anti-nodes of said bus coupling resonator, said resonator pump having a drive line and pairs of opposing pump coupling capacitors coupled to anti-nodes of the bus coupling resonator and a waveguide positioned between each pair of pump coupling capacitors;

(iv) a first Superconducting-Quantum-Interference-Device (SQUID) joined to an end of the first row of voltage nodes and anti-nodes of the bus coupling resonator; and

(v) a second Superconducting-Quantum-Interference-Device (SQUID) joined to an end of the second row of voltage nodes and anti-nodes of the bus coupling resonator;

(b) a qubit chip, comprising:

(i) a planar substrate with a plurality of qubit chip surface bonding elements with a distribution corresponding to said bonding elements of said wiring chip;

(ii) a first row of a plurality of qubits inductively coupled to a first probe line; and

(iii) a second row of a plurality of qubits inductively coupled to a second probe line;

(c) wherein said qubit chip is mounted to said wiring chip with the wiring chip and qubit surface bonding elements to produce a superconducting quantum processor unit.

17. The apparatus of claim 16 , said first probe line and said second probe line further comprising:

a Purcell filter; and

a parallel capacitor.

18. The apparatus of claim 16 , wherein each of said qubits comprises:

a transmon; and

a meandering readout resonator with a readout capacitor engaged with the transmon at one end and coupled to the first or second probe line at the other with an inductive coupling;

wherein said readout resonator is configured to produce a set resonator frequency.

19. The apparatus of claim 18 , wherein each transmon comprises:

a qubit pad with a qubit ground capacitor;

a bus coupling capacitor;

a qubit XY control; and

a qubit Z control.

20. The apparatus of claim 16 , wherein said bonding elements of said qubit chip and said wiring chip comprise superconducting indium metal pillars distributed around the planar substrates of the qubit chip and the wiring chip for crosstalk suppression.

Assignments (2)
CONFIRMATORY LICENSE Recorded May 18, 2022
From: UNIVERSITY OF CALIF-LAWRENC BERKELEY LAB
To: UNITED STATES DEPARTMENT OF ENERGY
Reel/Frame 059948/0907 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2022
From: SIDDIQI, IRFAN; LUO, JIE; MARINELLI, BRIAN
To: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
Reel/Frame 058560/0531 →
Continuity (2)
Provisional Application 63109516 · Nov 4, 2020
Related Publication 20220138611A1 · May 5, 2022
References Cited (9)
US 9858531B1 · Monroe · 2018 [cited by applicant]
US 9922289B2 · Abdo · 2018 [cited by examiner]
US 20140097405A1 · Bunyk · 2014 [cited by applicant]
US 20220058508A1 · Srinivasan · 2022 [cited by examiner]
Britt, Keith A. et al., “High-Performance Computing with Quantum Processing Units”, ACM Journal on Emerging Technologies in Computing Systems, vol. 1, No. 1, Article 1, Feb. 2017, pp. 1-13. [cited by applicant]
Grumbling, Emily et al., “Quantum Computing Progress and Prospects”, The National Academies of Sciences Engineering Medicine, The National Academies Press, 2019, pp. 1-273. [cited by applicant]
Luo, Jie, “Advanced Quantum Testbed Program”, First Annual Stakeholder Meeting, QNL 3D Reconfigurable QPU and Processes R&D, Jun. 10, 2020, pp. 1-13. [cited by applicant]
Luo, Jie, “Integrating Quantum Optical and Superconducting Circuits with Quantum Acoustics for Scalable Quantum Network and Computation”, California Institute of Technology, Pasadena, California, Thesis In Partial Fulli… [cited by applicant]
Preskill, John, “Quantum Computing in the NISQ era and beyond”, Institute for Quantum Information and Matter and Walker Burke Institute for Theotrical Physics California Institute of Technology, Pasadena, CA 91125, Jul.… [cited by applicant]
Cited By (1)
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