Semiconductor device including shared sense amplification circuit group
A semiconductor device is provided. The semiconductor device includes a plurality of memory cell groups and a plurality of sense amplification unit groups, and at least two memory cell groups share a same sense amplification unit group.
1. A semiconductor device, comprising a plurality of memory cell groups and a plurality of sense amplification circuit groups, at least two memory cell groups sharing a same sense amplification circuit group; and no sense amplification circuit group is arranged between the two memory cell groups;
wherein each memory cell group comprises a plurality of bit lines, each sense amplification circuit group comprises a plurality of sense amplification circuits, and each sense amplification circuit is electrically connected to a respective one of the bit lines;
wherein the plurality of sense amplification circuit groups are respectively located on two sides of the two memory cell groups away from each other; and
wherein the sense amplification circuits are alternately distributed relative to the bit lines.
2. The semiconductor device of claim 1 , wherein each sense amplification circuit group acts on at least two memory cell groups.
3. The semiconductor device of claim 1 , wherein the semiconductor device further comprises a plurality of selection switch groups, each sense amplification circuit group is electrically connected to the memory cell groups through a respective one of the selection switch groups.
4. The semiconductor device of claim 3 , wherein each selection switch group comprises a plurality of selection switches, and each sense amplification circuit is electrically connected to the bit lines through a respective one of the selection switches.
5. The semiconductor device of claim 3 , wherein each selection switch group is arranged between two memory cell groups.
6. The semiconductor device of claim 5 , wherein the two memory cell groups share a same sense amplification circuit group.
7. The semiconductor device of claim 4 , wherein each selection switch comprises an N-channel Metal Oxide Semiconductor (NMOS) transistor and a P-channel Metal Oxide Semiconductor (PMOS) transistor, and each of the NMOS transistor and the PMOS transistor is electrically connected to a respective one of the bit lines in different memory cell groups.
8. The semiconductor device of claim 7 , wherein a gate of the NMOS transistor is electrically connected to a gate of the PMOS transistor.
9. The semiconductor device of claim 8 , wherein each of the NMOS transistor and the PMOS transistor is electrically connected to a respective one of the sense amplification circuits through a wire, and the wire passes through a posterior conductive interconnection layer.
10. The semiconductor device of claim 6 , wherein each sense amplification circuit corresponds to a respective one of the bit lines and a respective one of the selection switches.