Voltage level shifting with reduced timing degradation
An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.
1. An apparatus, comprising:
a first field effect transistor (FET) comprising an n-channel metal oxide semiconductor (NMOS) FET, including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and
a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails,
wherein the first and second voltage rails are configured to receive first and second supply voltages in accordance with the second voltage domain, respectively, and further
wherein the NMOS FET and the first inverter are coupled in series in that order between the first voltage rail and the second voltage rail.
2. The apparatus of claim 1 , wherein the second input signal varies between a first low logic voltage and a first high logic voltage in accordance with the second voltage domain, wherein the first supply voltage is substantially the same as the first high logic voltage, and wherein the second supply voltage is substantially the same as the first low logic voltage.
3. The apparatus of claim 2 , wherein the first input signal varies between a second low logic voltage and a second high logic voltage in accordance with the first voltage domain, wherein the second low logic voltage is substantially the same as the first high logic voltage.
4. The apparatus of claim 1 , wherein the first input signal is logically complementary to the second input signal.
5. The apparatus of claim 1 , further comprising a latch coupled to the first output of the first inverter.
6. The apparatus of claim 1 , wherein the first gate of the first FET is configured to receive the first input signal, and the first inverter is configured to receive the second input signal and generate the first output signal in accordance with a first mode of operation.
7. A method, comprising:
receiving, at a first input, a first input signal that varies in accordance with a first voltage domain in accordance with a first mode of operation;
receiving, at a second input, a second input signal that varies in accordance with a second voltage domain in accordance with the first mode of operation, wherein the first voltage domain is different than the second voltage domain;
generating, at an output, a first output signal that varies in accordance with the second voltage domain in accordance with the first mode of operation, wherein the first output signal is based on the first and second input signals;
receiving, at the first input, a third input signal that varies in accordance with a third voltage domain in accordance with a second mode of operation;
receiving, at the second input, a fourth input signal that varies in accordance with the third voltage domain in accordance with the second mode of operation; and
generating, at the output, a second output signal that varies in accordance with the third voltage domain in accordance with the second mode of operation, wherein the second output signal is based on the third and fourth input signals.
8. The method of claim 7 , wherein the first input signal is logically complementary to the second input signal.
9. The method of claim 7 , wherein the first input signal varies between a first low logic voltage and a first high logic voltage in accordance with the first voltage domain, wherein the second input signal varies between a second low logic voltage and second high logic voltage in accordance with the second voltage domain, and wherein the second high logic voltage is substantially the same as the first low logic voltage.
10. The method of claim 7 , wherein the first input signal varies between a first low logic voltage and a first high logic voltage in accordance with the first voltage domain, wherein the second input signal varies between a second low logic voltage and second high logic voltage in accordance with the second voltage domain, and wherein the first high logic voltage is substantially the same as the second low logic voltage.