IP Library › Granted Patent US 11,749,654
Granted Patent B2
US 11,749,654 · App. 17/521,750 · Granted Sep 5, 2023

Semiconductor device and method of manufacturing semiconductor device

Inventors: Gi Tae Lim (Incheon, KR); Jae Yun Kim (Incheon, KR); Myung Jea Choi (Incheon, KR)
Assignee: Amkor Technology Singapore Holding Pte. Ltd.
H01L25/105H01L21/52H01L21/56H01L23/3128H01L23/49822H01L23/49838H01L23/5386H01L24/16H01L24/48H01L2224/16227H01L2224/48227H01L2225/1058
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Quick Facts
Patent No.
US 11,749,654
App. No.
17/521,750
Granted
Sep 5, 2023
Kind
B2
Abstract

In one example, a semiconductor structure comprises a redistribution structure comprising a conductive structure, a cavity substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure, an electronic component on the top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure, and an encapsulant in the cavity and on the top side of the redistribution structure, contacting a lateral side of the electronic component, a lateral side of the cavity, and a lateral side of the pillar. Other examples and related methods are also disclosed herein.

Claims (48)

1. A semiconductor structure, comprising:

a first semiconductor device comprising:

a redistribution structure comprising a conductive structure;

a first substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure;

an electronic component on a top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure via a component interconnect; and

an encapsulant in the cavity and on the top side of the redistribution structure bounding a lateral side of the electronic component and the pillar; and

a second semiconductor device on a top side of the first semiconductor device, wherein the second semiconductor device is electrically coupled with a substrate land on a top side of the first substrate;

wherein the encapsulant comprises a single continuous structure between an active side of the electronic component and the redistribution structure.

2. The semiconductor structure of claim 1 , wherein the second semiconductor device comprises a second substrate, a second electronic component on a top side of the second substrate, and a second encapsulant on the top side of the second substrate contacting a lateral side of the second electronic component.

3. The semiconductor structure of claim 1 , wherein the redistribution structure comprises a redistribution layer substrate, and the first substrate comprises a pre-formed substrate.

4. The semiconductor structure of claim 1 , wherein the pillar of the first semiconductor device comprises a conductive post electrically coupled with the conductive structure of the redistribution structure and the substrate land.

5. The semiconductor structure of claim 1 , wherein the first substrate bounds the electronic component on at least two lateral sides.

6. The semiconductor structure of claim 1 , wherein the encapsulant is between the electronic component and the redistribution structure and between the first substrate and the redistribution structure.

7. The semiconductor structure of claim 1 , wherein the encapsulant contacts a lateral side of component interconnect and a lateral side of the pillar.

8. A method to manufacture a semiconductor structure, comprising:

providing a first semiconductor device comprising:

a redistribution structure comprising a conductive structure;

a first substrate on a top side of the redistribution structure and having a cavity and a pillar contacting the redistribution structure;

an electronic component on a top surface of the redistribution structure and in the cavity, wherein the electronic component is electrically coupled with the conductive structure via a component interconnect; and

an encapsulant in the cavity and on the top side of the redistribution structure bounding a lateral side of the electronic component and the pillar; and

providing a second semiconductor device on a top side of the first semiconductor device, wherein the second semiconductor device is electrically coupled with a substrate land on a top side of the first substrate;

wherein the encapsulant comprise a single continuous structure between an active side of the electronic component and the redistribution structure.

9. The method of claim 8 , wherein the second semiconductor device comprises:

a second substrate;

a second electronic component on a top side of the second substrate; and

a second encapsulant on the top side of the second substrate contacting a lateral side of the second electronic component.

10. The method of claim 8 , wherein:

the redistribution structure comprises a redistribution layer substrate; and

the first substrate comprises a pre-formed substrate.

11. The method of claim 8 , wherein the pillar of the first semiconductor device comprises a conductive post electrically coupled with the conductive structure of the redistribution structure and the substrate land.

12. The method of claim 8 , wherein the first substrate bounds the electronic component on at least two lateral sides.

13. The method of claim 8 , wherein the encapsulant is between the electronic component and the redistribution structure and between the first substrate and the redistribution structure.

14. The method of claim 8 , wherein the encapsulant contacts a lateral side of component interconnect and a lateral side of the pillar.

15. A semiconductor structure, comprising:

a redistribution structure comprising a first conductive structure and a second conductive structure;

a cavity substrate over the redistribution structure, wherein the cavity substrate has a cavity and a substrate interconnect coupled with the first conductive structure;

an electronic component over the redistribution structure and in the cavity, wherein the electronic component has a component interconnect coupled with the first conductive structure; and

an encapsulant over the redistribution structure and in the cavity, wherein the encapsulant contacts a lateral side of the electronic component;

wherein the first conductive structure is within the redistribution structure and a first portion of the second conductive structure extends external to the redistribution structure; and

wherein the encapsulant comprises a single continuous structure between an active side of the electronic component and the redistribution structure.

16. The semiconductor structure of claim 15 , further comprising an external interconnect coupled with the first portion of the second conductive structure that is external to the redistribution structure.

17. The semiconductor structure of claim 15 , wherein the first conductive structure is coupled with the second conductive structure.

18. The semiconductor structure of claim 15 , wherein the redistribution structure comprises a first dielectric structure and a second dielectric structure.

19. The semiconductor structure of claim 18 , wherein the first conductive structure is between the first dielectric structure and the second dielectric structure.

20. The semiconductor structure of claim 15 , wherein the component interconnect has a single width, and the single width of the component interconnect is less than a width of the substrate interconnect.

21. The semiconductor structure of claim 15 , wherein the substrate interconnect comprises a copper post.

22. The semiconductor structure of claim 15 , wherein the encapsulant is between the redistribution structure and the cavity substrate.

23. The semiconductor structure of claim 15 , wherein the encapsulant contacts a lateral side of component interconnect and a lateral side of the substrate interconnect.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 27, 2021
From: AMKOR TECHNOLOGY KOREA, INC.
To: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Reel/Frame 058546/0473 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2021
From: LIM, GI TAE; KIM, JAE YUN; CHOI, MYUNG JAE
To: AMKOR TECHNOLOGY KOREA, INC.
Reel/Frame 058059/0540 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 9, 2021
From: AMKOR TECHNOLOGY KOREA, INC.
To: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
Reel/Frame 058841/0827 →
Continuity (2)
Continuation 16530305 · Aug 2, 2019
Related Publication 20220068897A1 · Mar 3, 2022