Semiconductor device with CMOS process based hall sensor and manufacturing method
A semiconductor device including a CMOS process-based Hall sensor is provided. The semiconductor device which may include a N-type sensing region which is formed on a semiconductor substrate; P-type contact regions and N-type contact regions which are alternately formed in the N-type sensing region; a plurality of first trenches which are formed in contact with the P-type contact regions and have a first width; and a plurality of second trenches which separate the P-type contact regions and the N-type contact regions and have a second width less than the first width.
1. A semiconductor device, comprising:
a N-type sensing region disposed on a semiconductor substrate;
P-type contact regions and N-type contact regions which are disposed alternately in the N-type sensing region;
at least one first trench, disposed adjacent to at least one of the P-type contact regions, and configured to have a first width; and
a plurality of second trenches, which are configured to separate each of the P-type contact regions and each of the N-type contact regions, and are configured to have a second width less than the first width of the at least one first trench,
wherein a width of each of the N-type contact regions is less than a width of each of the P-type contact regions, and
wherein each of the P-type contact regions is configured to have a same width as each other.
2. The semiconductor device of claim 1 , wherein each of the N-type contact regions is disposed to extend outward beyond a first boundary and a second boundary of the N-type sensing region to a surface of the semiconductor substrate.
3. The semiconductor device of claim 1 , further comprising one or more dummy contact regions which are disposed on at least one of a first outer portion and a second outer portion of at least one of the N-type contact regions.
4. The semiconductor device of claim 1 , wherein a depth of each of the N-type contact regions is less than a depth of the at least one first trench.
5. The semiconductor device of claim 1 , wherein a doping concentration of the N-type sensing region is less than a doping concentration of each of the N-type contact regions.
6. The semiconductor device of claim 1 , wherein each of the N-type contact regions is disposed parallel to each other in a straight line on the N-type sensing region.
7. The semiconductor device of claim 1 , wherein a doping concentration of the N-type sensing region is between 3.0E16/cm 3 and 4.0E16/cm 3 , and a depth to which the doping concentration is 1.5E15/cm 3 is between 2 μm and 5 μm.
8. The semiconductor device of claim 1 , wherein a doping concentration of a surface of the N-type sensing region is between 8.0E15/cm 3 and 1.5E16/cm 3 , and a depth to which the doping concentration is 1.5E15/cm 3 is between 5 μm and 8 μm.
9. The semiconductor device of claim 1 , wherein a doping concentration of a conductive dopant within a preset distance from a first side and a second side with respect to a center of a PN junction formed between the P-type contact region and the N-type sensing region is equal to or greater than 9.0 E15/cm 3 .
10. A semiconductor device, comprising:
a planar Hall sensor and a vertical Hall sensor disposed on a semiconductor substrate,
wherein the vertical Hall sensor comprises:
a first N-type sensing region disposed on the semiconductor substrate;
one or more first N-type contact regions disposed in the first N-type sensing region;
a plurality of first P-type contact regions disposed in the first N-type sensing region;
a plurality of first trenches configured to surround the first N-type sensing region; and
a plurality of second trenches configured to surround each of the one or more first N-type contact regions,
wherein a width of each of the plurality of second trenches is less than a width of each of the plurality of first trenches,
wherein a width of each of the one or more first N-type contact regions is less than a width of each of the plurality of first P-type contact regions, and
wherein each of the plurality of first P-type contact regions is configured to have a same width as each other.
11. The semiconductor device of claim 10 , wherein the planar Hall sensor comprises:
a second N-type sensing region disposed on the semiconductor substrate;
one or more second N-type contact regions disposed in the second N-type sensing region;
a second P-type contact region disposed in the second N-type sensing region;
a plurality of third trenches configured to surround the second N-type sensing region; and
a plurality of fourth trenches configured to surround each of the one or more second N-type contact regions,
wherein a width of each of the one or more second N-type contact regions is less than a width of the second P-type contact region.
12. The semiconductor device of claim 11 , wherein the width of the one or more second N-type contact regions disposed in the planar Hall sensor is greater than the width of the one or more first N-type contact regions disposed in the vertical Hall sensor.
13. The semiconductor device of claim 10 , wherein the vertical Hall sensor comprises:
a first vertical Hall sensor, configured to measure an X-axis magnetic field parallel to a surface of the substrate; and
a second vertical Hall sensor, configured to measure a Y-axis magnetic field parallel to the surface of the substrate,
wherein the planar Hall sensor is configured to measure a magnetic field perpendicular to the substrate surface, and
wherein the first vertical Hall sensor and the second vertical Hall sensor are configured to be disposed adjacent to the planar Hall sensor.
14. The semiconductor device of claim 11 , wherein the one or more first N-type contact regions are disposed to extend outward beyond a first boundary and a second boundary of the first N-type sensing region to a surface of the semiconductor substrate.
15. The semiconductor device of claim 11 , wherein the plurality of third trenches are disposed to be in contact with the one or more second N-type contact regions.
16. A semiconductor device, comprising:
a vertical Hall sensor disposed on a substrate; and
a planar Hall sensor disposed on the substrate;
wherein the vertical Hall sensor comprises:
a plurality of P-type contact regions;
at least one N-type contact region; and
a first dummy contact region and a second dummy contact region respectively disposed at a first end and a second end of the at least one N-type contact region;
wherein a width of each of the at least one N-type contact region is less than a width of each of the plurality of P-type contact regions, and
wherein each of the plurality of P-type contact regions is configured to have a same width as each other.
17. The semiconductor device of claim 16 , further comprising:
at least one first trench disposed at a first end of at least one of the plurality of P-type contact regions, and
second trenches disposed to surround each of the at least one N-type contact region.
18. The semiconductor device of claim 17 , wherein a width of the at least one first trench is greater than a width of each of the second trenches.
19. The semiconductor device of claim 17 , further comprising a N-type sensing region disposed on the substrate,
wherein the at least one N-type contact region is disposed to extend outward beyond a first boundary and a second boundary of the N-type sensing region to a surface of the substrate.