Capacitor array structure and method for forming same

1. A method for forming a capacitor array structure, comprising:

forming a base, the base comprising a substrate, a stack structure located on the substrate and a mask layer located on the stack structure, in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided in the mask layer;

etching the stack structure along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate;

forming a conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer;

removing the conductive layer that covers the top surface of the mask layer and is located in the etching window with a first dry etching process to expose the mask layer; and

removing the mask layer, the conductive layer remaining in the capacitor hole forming a lower electrode;

wherein a top surface of the conductive layer remaining in the capacitor hole is flush with a top surface of the stack structure by controlling an etching parameter of the first dry etching process.

2. The method for forming a capacitor array structure of claim 1 , wherein forming the base comprises:

providing the substrate;

alternately depositing support layers and sacrificial layers on a surface of the substrate to form the stack structure;

forming the mask layer at a surface of the stack structure; and

patterning the mask layer to form the etching window in the mask layer, the etching window penetrating the mask layer along the direction perpendicular to the substrate.

3. The method for forming a capacitor array structure of claim 2 , wherein forming the stack structure comprises:

depositing a bottom support layer of the support layers on the surface of the substrate;

depositing a first sacrificial layer of the sacrificial layers on a surface of the bottom support layer;

depositing an intermediate support layer of the support layers on a surface of the first sacrificial layer;

depositing a second sacrificial layer of the sacrificial layers on a surface of the intermediate support layer; and

depositing a top support layer of the support layers on a surface of the second sacrificial layer.

4. The method for forming a capacitor array structure of claim 2 , wherein a material of the support layers comprises a nitride material, and a material of the sacrificial layers comprises an oxide material.

5. The method for forming a capacitor array structure of claim 1 , wherein etching the stack structure along the etching window comprises:

etching the stack structure along the etching window with a second-first dry etching process.

6. The method for forming a capacitor array structure of claim 1 , wherein the etching parameter comprises an etching time.

7. The method for forming a capacitor array structure of claim 1 , wherein an etching selection ratio of a first dry etchant used in the first dry etching process between the conductive layer and the mask layer is greater than 2.

8. The method for forming a capacitor array structure of claim 1 , wherein a material of the conductive layer comprises TiN, and a material of the mask layer comprise polysilicon.

9. The method for forming a capacitor array structure of claim 1 , wherein a first dry etchant used in the first dry etching process comprises a mixed gas of Cl 2 and BCl 3 .

10. The method for forming a capacitor array structure of claim 9 , wherein removing the mask layer comprises:

removing the mask layer with a third dry etching process.

11. The method for forming a capacitor array structure of claim 10 , wherein an etching selection ratio of a second dry etchant used in the third dry etching process between the mask layer and the conductive layer is greater than 10.

12. The method for forming a capacitor array structure of claim 11 , wherein the etching selection ratio of the second dry etchant between the mask layer and the conductive layer is greater than an etching selection ratio of the first dry etchant between the conductive layer and the mask layer.

13. The method for forming a capacitor array structure of claim 11 , wherein the second dry etchant used in the third dry etching process comprises a mixed gas of HBr and Cl 2 .

14. The method for forming a capacitor array structure of claim 1 , further comprising:

cleaning the top surface of the stack structure and a top surface of the lower electrode after removing the mask layer.

15. The method for forming a capacitor array structure of claim 1 , wherein a portion of the mask layer is removed with the first dry etching process.

16. A method for forming a capacitor array structure, comprising:

forming a base, the base comprising a substrate, a stack structure located on the substrate and a mask layer located on the stack structure, in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided in the mask layer;

etching the stack structure along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate;

forming a conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer;

removing the conductive layer that covers the top surface of the mask layer and is located in the etching window with a dry etching process to expose the mask layer; and

removing the mask layer, the conductive layer remaining in the capacitor hole forming a lower electrode;

wherein an etching selection ratio of a dry etchant used in the dry etching process between the conductive layer and the mask layer is greater than 2.

17. A method for forming a capacitor array structure, comprising:

forming a base, the base comprising a substrate, a stack structure located on the substrate and a mask layer located on the stack structure, in which an etching window that penetrates the mask layer in a direction perpendicular to the substrate is provided in the mask layer;

etching the stack structure along the etching window to form a capacitor hole that penetrates the stack structure along the direction perpendicular to the substrate;

forming a conductive layer that fills up the capacitor hole and the etching window and covers a top surface of the mask layer;

removing the conductive layer that covers the top surface of the mask layer and is located in the etching window with a first dry etching process to expose the mask layer; and

removing the mask layer with a second dry etching process, the conductive layer remaining in the capacitor hole forming a lower electrode.