Power ramping sequence control for a memory device
Memory devices are disclosed that support multiple power ramping sequences or modes. For example, a level shifter device is operably connected to a memory macro in a memory device. The level shifter device receives at least one gating signal. Based on a state of the at least one gating signal, the level shifter device outputs one or more signals that cause or control voltage signals in or received by the memory macro to ramp up, ramp down, or ramp up and ramp down according to one or more power ramping modes.
1. A device, comprising:
a memory macro configured to receive a first voltage signal and a second voltage signal, the memory macro including power management circuitry; and
a level shifter device configured to provide a third signal to the power management circuitry to control the first and the second voltage signals in the memory macro based on a fourth signal, wherein:
the first voltage signal is ramped up before the second voltage signal is ramped up when the fourth signal has a first logic state; and
the second voltage signal is ramped up before the first voltage signal is ramped up when the fourth signal has a second logic state.
2. The device of claim 1 , wherein the memory macro comprises a static random-access macro, the static random-access macro comprising a static random access memory array and periphery circuitry.
3. The device of claim 2 , wherein the periphery circuitry comprises header circuits that are operably connected to respective power management circuits in the power management circuitry.
4. The device of claim 1 , wherein the first voltage signal is a VDD voltage signal and the second voltage signal is a VDDM voltage signal.
5. The device of claim 1 , wherein the level shifter device is configured to combine multiple power ramping modes simultaneously.
6. The device of claim 1 , wherein the level shifter device is configured to produce a shutdown signal.
7. The device of claim 1 , wherein the level shifter device is configured to produce a shutdown signal and a sleep signal.
8. The device of claim 1 , wherein the level shifter device is configured to cause the first voltage signal to float in a bulk off mode.
9. The device of claim 1 , wherein the level shifter device comprises four level shifter circuits, where one level shifter circuit outputs a shutdown signal and three level shifter circuits each output a sleep signal.
10. A method, comprising:
receiving, at a level shifter device operably connected to a memory macro, a gating signal;
based on a signal level of the gating signal having a first logic state:
causing a first power ramping mode in a plurality of power ramping modes to be produced in the memory macro; and
causing a second power ramping mode in the plurality of power ramping modes to be produced in the memory macro after the first power ramping mode;
wherein
the first power ramping mode ramps up a first voltage signal before a second voltage signal is ramped up and ramps down the second voltage signal before the first voltage signal is ramped down; and
the second power ramping mode ramps up the second voltage signal before the first voltage signal is ramped up and ramps down the first voltage signal before the second voltage signal is ramped down.
11. The method of claim 10 , wherein:
the first power ramping mode ramps up a first voltage signal before a second voltage signal is ramped up; and
the second power ramping mode ramps up the second voltage signal before the first voltage signal is ramped up.
12. The method of claim 10 , further comprising combining, by level shifter device, multiple power ramping modes simultaneously.
13. The method of claim 10 , further comprising causing, by the level shifter device, the first voltage signal to float in a bulk off mode.
14. An electronic device, comprising:
a power supply;
a memory macro operably connected to the power supply and configured to receive a first voltage signal and a second voltage signal, the memory macro comprising power management circuitry operable to cause the first and the second voltage signals to ramp up and ramp down according to at least one power ramping mode that is included in a plurality of power ramping modes; and
a level shifter device operably connected to the power management circuitry in the memory macro and to the power supply and configured to provide one or more signals to the power management circuitry that support the plurality of power ramping modes;
wherein:
the multiple power ramping modes comprise a first power ramping mode and a second power ramping mode;
the first power ramping mode causes a first voltage signal to ramp up before a second voltage signal is ramped up; and
the second power ramping mode causes the second voltage signal to ramp up before the first voltage signal is ramped up.
15. The electronic device of claim 14 , wherein the first voltage signal is a VDD voltage signal and the second voltage signal is a VDDM voltage signal.
16. The electronic device of claim 14 , wherein the level shifter device is configured to support a bi-directional mode power ramping mode that combines the first and the second power ramping modes.
17. The electronic device of claim 14 , wherein the memory macro comprises a static random-access macro.
18. The electronic device of claim 14 , wherein the level shifter device comprises multiple level shifter circuits that produce a shutdown signal and one or more sleep signals.
19. The electronic device of claim 14 , wherein the level shifter device is configured to produce at least one of a shutdown signal or a sleep signal.
20. The electronic device of claim 14 , wherein the level shifter device is configured to cause the first voltage signal to float in a bulk off mode.