Synchronous rectifier control circuit and method

1. A method for controlling a synchronous rectifier (SR) transistor of a flyback converter, the method comprising:

determining a first voltage across conduction terminals of the SR transistor;

asserting a turn-on signal when a body diode of the SR transistor is conducting current;

asserting a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold;

generating a gating signal based on an output voltage of the flyback converter and on the first voltage, wherein generating the gating signal comprises:

determining a reference voltage based on the output voltage;

when the first voltage increases above the reference voltage, deasserting the gating signal; and

while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage;

turning on the SR transistor based on the turn-on signal and on the gating signal; and

turning off the SR transistor based on the turn-off signal.

2. The method of claim 1 , wherein turning on the SR transistor comprises turning on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

3. The method of claim 1 , wherein the first delay time is lower than one quarter of a ringing time of the first voltage.

4. The method of claim 1 , wherein the first delay time is between 20 ns and 210 ns.

5. The method of claim 1 , wherein the reference voltage is given by

V ref =(1+ k )· V out ,

where V ref represents the reference voltage, V out represents the output voltage, and k is a number higher than o.

6. The method of claim 5 , wherein k is between 0.2 and 0.5.

7. The method of claim 1 , wherein generating the gating signal comprises using a gating circuit that comprises:

a first comparator having a first input for receiving the first voltage and a second input for receiving the reference voltage;

a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and

an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output for providing the gating signal.

8. The method of claim 1 , further comprising generating a blanking signal based on the first voltage, wherein turning on the SR transistor is further based on the blanking signal, and wherein turning off the SR transistor is further based on the blanking signal.

9. The method of claim 1 , wherein asserting the turn-on signal comprises asserting the turn-on signal when the first voltage drops below a second threshold, and wherein asserting the turn-off signal comprises asserting the turn-off signal when the first voltage increases above a third threshold.

10. The method of claim 1 , further comprising operating the flyback converter as a non-complementary active clamp flyback (ACF) converter.

11. The method of claim 1 , further comprising operating the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

12. A synchronous rectifier (SR) controller comprising:

an output terminal configured to be coupled to a control terminal of an SR transistor of a flyback converter; and

an input terminal configured to receive an output voltage of the flyback converter, wherein the SR controller is configured to:

determine a first voltage across conduction terminals of the SR transistor;

assert a turn-on signal when a body diode of the SR transistor is conducting current;

assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold;

generate a gating signal based on the output voltage of the flyback converter and on the first voltage, wherein the SR controller is configured to generate the gating signal by:

determining a reference voltage based on the output voltage,

when the first voltage increases above the reference voltage, deasserting the gating signal, and

while the gating signal is deasserted, comparing the first voltage with the reference voltage and asserting the gating signal a first delay time after the first voltage drops below the reference voltage;

turn on the SR transistor based on the turn-on signal and on the gating signal; and

turn off the SR transistor based on the turn-off signal.

13. The SR controller of claim 12 , wherein the SR controller is configured to turn on the SR transistor when the turn-on signal is asserted while the gating signal is deasserted.

14. The SR controller of claim 12 , further comprising a gating circuit configured to generate the gating signal, the gating circuit comprising:

a first comparator having a first input configured to receive the first voltage and a second input configured to receive the reference voltage;

a delay circuit having an input coupled to an output of the first comparator, the delay circuit having a delay time equal to the first delay time; and

an OR gate having a first input coupled to the output of the first comparator, a second input coupled to an output of the delay circuit, and an output configured to provide the gating signal.

15. The SR controller of claim 14 , further comprising;

a turn on circuit configured to generate the turn-on signal;

a turn-off circuit configured to generate the turn-off signal;

a first AND gate having a first input coupled to an output of the turn on circuit, and a second input coupled to an output of the OR gate; and

a first flip-flop having a first input coupled to an output of the first AND gate, a second input coupled to an output of the turn-off circuit, and an output coupled to the output terminal.

16. The SR controller of claim 15 , further comprising:

a blanking circuit having an input couple to the output of the first flip-flop; and

a second AND gate having a first input coupled to an output of the blanking circuit, a second input coupled to the output of the turn-off circuit, and an output coupled to the second input of the first flip-flop, wherein the first AND gate comprises a third input coupled to the output of the blanking circuit.

17. The SR controller of claim 15 , wherein the turn on circuit comprises a second comparator having a first input configured to receive a second threshold, and a second input configured to receive the first voltage; and wherein the turn off circuit comprises a third comparator having a first input configured to receive a third threshold, and a second input configured to receive the first voltage.

18. A flyback converter comprising:

a transformer having a first winding and a second winding;

an output terminal coupled to the second winding;

a first primary transistor coupled to the first winding;

a primary controller having an output coupled to a control terminal of the first primary transistor;

a synchronous rectifier (SR) transistor coupled to the second winding; and

an SR controller configured to:

determine a first voltage across conduction terminals of the SR transistor,

assert a turn-on signal when a body diode of the SR transistor is conducting current,

assert a turn-off signal when current flowing through the conduction terminals of the SR transistor decreases below a first threshold,

generate a gating signal based on an output voltage at the output terminal and on the first voltage, wherein the SR controller is configured to generate the gating signal by being configured to:

determine a reference voltage based on the output voltage,

when the first voltage increases above the reference voltage, deassert the gating signal, and

while the gating signal is deasserted, compare the first voltage with the reference voltage and assert the gating signal a first delay time after the first voltage drops below the reference voltage;

turn on the SR transistor based on the turn-on signal and on the gating signal; and

turn off the SR transistor based on the turn-off signal.

19. The flyback converter of claim 18 , further comprising a second primary transistor coupled to the first winding, wherein the primary controller is configured to control the first and second primary transistor to operate the flyback converter as a non-complementary active clamp flyback (ACF) converter.

20. The flyback converter of claim 18 , further comprising a resistor coupled to the first winding, a capacitor coupled in parallel with the resistor, and a diode coupled between the first primary transistor and the capacitor, wherein the primary controller is configured to control the first primary transistor to operate the flyback converter as an RCD clamp flyback converter in discontinuous conduction mode (DCM).

21. The flyback converter of claim 18 , wherein the SR transistor is a metal-oxide semiconductor field-effect transistor (MOSFET) or GaN transistor.