IP Library Granted Patent US 11,735,131
Granted Patent B2
US 11,735,131 · App. 17/523,976 · Granted Aug 22, 2023

Display device

Inventors: Shunpei Yamazaki (Setagaya, JP); Hajime Kimura (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3614G02F1/136286G09G3/3648H01L27/124H01L27/1225H01L27/1244H01L27/1262H01L29/66969H01L29/7869G02F1/1368G02F1/13685G02F1/133512G02F1/136295G09G2300/0417G09G2300/0426G09G2310/0297G09G2320/0223H01L21/0274H01L21/02565H01L21/02581H01L21/02631H01L21/02675H01L21/465H01L21/47635H01L21/67115H01L27/1255H01L27/1274H01L29/24
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Quick Facts
Patent No.
US 11,735,131
App. No.
17/523,976
Granted
Aug 22, 2023
Kind
B2
Abstract

A display device that is suitable for increasing in size is achieved. Three or more source lines are provided for each pixel column. Video signals having the same polarity are input to adjacent source lines during one frame period. Dot inversion driving is used to reduce a flicker, crosstalk, or the like.

Claims (41)

1. A display device comprising:

first to third pixels arranged in a first column;

fourth to sixth pixels arranged in a second column adjacent to the first column; and

first to third demultiplexers,

wherein the first to sixth pixels each comprise a liquid crystal element,

wherein the first and fourth pixels are electrically connected to a first gate line,

wherein the second and fifth pixels are electrically connected to a second gate line,

wherein the third and sixth pixels are electrically connected to a third gate line,

wherein the first and third pixels are electrically connected to a first source line,

wherein the second pixel is electrically connected to a second source line,

wherein the fourth and sixth pixels are electrically connected to a third source line,

wherein the fifth pixel is electrically connected to a fourth source line,

wherein the second and third source lines are positioned between the first and second columns,

wherein the first and fourth source lines are not positioned between the first and second columns,

wherein the first source line is electrically connected to the first demultiplexer,

wherein the second and third source lines are electrically connected to the second demultiplexer,

wherein the fourth source line is electrically connected to the third demultiplexer, and

wherein the second and third source lines supply signals having the same polarity.

2. The display device according to claim 1 , wherein the first to sixth pixels each comprise a transistor comprising an oxide semiconductor layer.

3. A display device comprising:

first to fourth pixels arranged in a first column;

fifth to eighth pixels arranged in a second column adjacent to the first column; and

first to third demultiplexers,

wherein the first and fifth pixels are electrically connected to a first gate line,

wherein the second and sixth pixels are electrically connected to a second gate line,

wherein the third and seventh pixels are electrically connected to a third gate line,

wherein the fourth and eighth pixel are electrically connected to a fourth gate line,

wherein the first pixel is electrically connected to a first source line,

wherein the third pixel is electrically connected to a second source line,

wherein the second pixel is electrically connected to a third source line,

wherein the fourth and fifth pixels are electrically connected to a fourth source line,

wherein the seventh pixel is electrically connected to a fifth source line,

wherein the sixth pixel is electrically connected to a sixth source line,

wherein the eighth pixel is electrically connected to a seventh source line,

wherein the third to fifth source lines are positioned between the first and second columns,

wherein the first to second and sixth to seventh source lines are not positioned between the first and second columns,

wherein the first and second source lines are electrically connected to the first demultiplexer,

wherein the third to fifth source lines are electrically connected to the second demultiplexer, and

wherein the sixth and seventh source lines are electrically connected to the third demultiplexer.

4. The display device according to claim 3 , wherein the first to sixth pixels each comprise a transistor comprising an oxide semiconductor layer.

5. The display device according to claim 3 , wherein the first to sixth pixels each comprise a liquid crystal element.

Priority Claims (1)
JP 2017-027901 · Feb 17, 2017 · national
Continuity (4)
Continuation 17146573 · Jan 12, 2021
Continuation 16720697 · Dec 19, 2019
Continuation 15891573 · Feb 8, 2018
Related Publication 20220068232A1 · Mar 3, 2022