Granted Patent B2

US 12,333,229 · App. 17/524,103 · Granted Jun 17, 2025

Inventor: Effendi Leobandung (Stormville, NY)

Assignee: International Business Machines Corporation

G06F30/33

Abstract

Claims (40)

1. An integrated circuit for validating logic key, the integrated circuit (IC) comprising:

key input circuit couple to a fuse check circuit, wherein the key input circuit includes at least, a plurality of XOR and XNOR logic gates and the key input circuit is for performing the steps of:

receiving a secret key from a user into the IC;

determining status of one or more antifuse circuit;

validating the secret key;

in responsive to the secret key not matching an original secret key, determining whether an antifuse threshold has been reached;

in responsive to determining that the antifuse threshold has been reached, disabling the IC, wherein disabling the IC based on unsuccessful attempts by an incorrect secret key;

in responsive to the secret key matching the original secret key, enabling the IC; and

in responsive to determining that the antifuse threshold has not been reached, activating the one or more antifuse circuit;

charge pump circuit coupled to the fuse check circuit and a switch matrix, wherein the fuse check circuit is a comparator circuit and the charge pump circuit is a voltage doubler circuit; and

the one or more antifuse circuit connected to the switch matrix.

2. The integrated circuit of claim 1 , wherein the fuse check circuit is configured to determine antifuse threshold.

3. The integrated circuit of claim 1 , wherein the charge pump circuit configured to increase an activate antifuse signal.

4. The integrated circuit of claim 3 , wherein the switch matrix is configured to activate the one or more antifuse circuit based on the activate antifuse signal.

5. The integrated circuit of claim 1 , wherein the switch matrix is a matrix circuit.

6. The integrated circuit of claim 1 , wherein the one or more antifuse circuit is made from thin oxide.

7. A method for validating logic key in an IC (integrated circuit), the method comprising:

key input circuit couple to a fuse check circuit, wherein the key input circuit includes at least, a plurality of XOR and XNOR logic gates and the key input circuit is for performing the steps of:

receiving a secret key from a user into the IC;

determining status of one or more antifuse circuit;

validating the secret key;

in responsive to the secret key not matching an original secret key, determining whether an antifuse threshold has been reached;

in responsive to determining that the antifuse threshold has been reached, disabling the IC, wherein disabling the IC based on unsuccessful attempts by an incorrect secret key;

in responsive to the secret key matching the original secret key, enabling the IC; and

in responsive to determining that the antifuse threshold has not been reached, activating the one or more antifuse circuit;

charge pump circuit coupled to the fuse check circuit and a switch matrix, wherein the fuse check circuit is a comparator circuit and the charge pump circuit is a voltage doubler circuit; and

the one or more antifuse circuit connected to the switch matrix.

8. The method of claim 7 , wherein determining status of one or more antifuse circuit further comprising:

determining, by fuse check circuit, the antifuse threshold.

9. The method of claim 7 , wherein validating the secret key further comprising:

determining, by the key input circuit, whether the secret key from the user matches the original secret key.

10. The method of claim 7 , wherein determining whether antifuse threshold has been reached further comprising:

comparing, by the fuse check circuit, whether a counter value exceed the antifuse threshold.

11. The method of claim 7 , wherein the antifuse threshold is a total number of antifuse circuit in the IC.

12. The method of claim 7 , wherein activating the one or more antifuse circuit further comprising:

incrementing a counter; and

blowing, by a charge pump circuit and switch matrix, a remaining antifuse of the one or more antifuse circuit.

13. The method of claim 12 , wherein switch matrix is a matrix.

14. The method of claim 7 , wherein one or more antifuse circuit is made from a thin oxide.

15. The method of claim 7 , wherein enabling the IC is allowing the IC to function normally.

Assignments (1)

Continuity (1)

References Cited (9)