Selective deposition on metals using porous low-k materials
A method is presented for selective deposition on metals using porous low-k materials. The method includes forming alternating layers of a porous dielectric material and a first conductive material, forming a surface aligned monolayer (SAM) over the first conductive material, depositing hydroxamic acid (HA) material over the porous dielectric material, growing an oxide material over the first conductive material, removing the SAM, depositing a dielectric layer adjacent the oxide material, and replacing the oxide material with a second conductive material defining a bottom electrode.
1 . A method comprising:
forming alternating layers of a porous dielectric material and a first conductive material;
patterning the alternating layers of the porous dielectric material and the first conductive material;
depositing hydroxamic acid (HA) material over the alternating layers of the porous dielectric material and the first conductive material, the HA material forming a surface aligned monolayer (SAM) over the first conductive layer;
selectively growing an oxide material over the SAM on the first conductive material;
depositing a dielectric layer adjacent the oxide material;
removing the SAM and the oxide material; and
depositing a second conductive material on the first conductive material defining a bottom electrode.
2 . The method of claim 1 , wherein the oxide material includes zinc oxide (ZnO) or aluminum oxide (AlOx).
3 . The method of claim 2 , wherein the oxide material is grown over the first conductive material at a temperature of about 150° C.
4 . The method of claim 1 , wherein the bottom electrode is tantalum nitride (TaN).
5 . The method of claim 1 , wherein the HA material extends into pores of the porous dielectric material.
6 . The method of claim 1 , wherein the HA material produces a film on the porous dielectric material that prevents thermal atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.
7 . The method of claim 1 , wherein the HA material has a carbon-rich composition exhibiting inhibitory properties.
8 . The method of claim 1 , wherein the oxide material is deposited in a Magnetic Random Access Memory (MRAM), a Resistive Random Access Memory (RRAM) or Phase Change Memory (PCM) area of a chip.
9 . A method comprising:
forming alternating layers of a porous dielectric material and a first conductive material;
patterning the alternating layers of the porous dielectric material and the first conductive material;
depositing hydroxamic acid (HA) material over the alternating layers of the porous dielectric material and the first conductive material, the HA material deposited over the first conductive material forming a surface aligned monolayer (SAM);
applying irradiation to one or more portions of the first conductive material to produce SAM HA cross-linking;
selectively growing an oxide material over the SAM on the first conductive material including a non-irradiated portion of the SAM;
depositing a dielectric layer adjacent the oxide material;
removing the non-irradiated portion of the SAM and the oxide material; and
depositing a second conductive material on the first conductive material defining a bottom electrode.
10 . The method of claim 9 , wherein the oxide material includes zinc oxide (ZnO) or aluminum oxide (AlOx).
11 . The method of claim 10 , wherein the oxide material is grown over the first conductive material at a temperature of about 150° C.
12 . The method of claim 9 , wherein the bottom electrode is tantalum nitride (TaN).
13 . The method of claim 9 , wherein the HA material extends into pores of the porous dielectric material.
14 . The method of claim 9 , wherein the HA material produces a film on the porous dielectric material that prevents thermal atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes.
15 . The method of claim 9 , wherein the HA material has a carbon-rich composition exhibiting inhibitory properties.
16 . The method of claim 9 , wherein the oxide material is deposited in a Magnetic Random Access Memory (MRAM), a Resistive Random Access Memory (RRAM) or Phase Change Memory (PCM) area of a chip.
17 . The method of claim 9 , wherein the irradiation is applied by e-beam exposure.
18 . The method of claim 9 , wherein the irradiation is applied by extreme ultraviolet (EUV) exposure.