IP Library Granted Patent US 8,242,019
Granted Patent B2
US 8,242,019 · App. 12/414,917 · Granted Aug 14, 2012

Selective deposition of metal-containing cap layers for semiconductor devices

Assignee: Tokyo Electron Limited
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Quick Facts
Patent No.
US 8,242,019
App. No.
12/414,917
Granted
Aug 14, 2012
Kind
B2
Abstract

A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a patterned substrate containing metal surfaces and dielectric layer surfaces, and modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, where the modifying substitutes a hydrophilic functional group in the dielectric layer surfaces with a hydrophobic functional group. The method further includes depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor.

Claims (22)

1. A method of forming a semiconductor device, comprising:

providing a patterned substrate containing metal surfaces and dielectric layer surfaces;

modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, the modifying substituting a hydrophilic functional group in the dielectric layer surfaces with the hydrophobic functional group; and

depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor, wherein the depositing comprises:

exposing the modified dielectric layer surfaces and the metal surfaces to the metal-containing precursor vapor to deposit metal layers selectively on the metal surfaces, wherein the metal-containing precursor vapor contains a metal element selected from platinum (Pt), gold (Au), ruthenium (Ru), cobalt (Co), tungsten (W), rhodium (Rh), iridium (Ir), or palladium (Pd), or a combination of two or more thereof, and

incorporating a dopant into the metal layers by exposing the deposited metal layers to a dopant gas selected from PH 3 , BH 3 , B 2 H 6 , BF 3 , NF 3 , NH 3 , N 2 , N 2 H 4 , PF 3 , PBr 3 , BCl 3 , Bl 3 , SiH 4 , Si 2 H 6 , SiH 3 Cl, SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , Si 2 Cl 6 , SiH 3 F, SiH 2 F, SiHF 3 , SiF 4 , Si 2 F 6 , GeH 4 , or GeCl 4 , or a combination of two or more thereof, wherein the incorporating comprises exposing the metal layers to a gas cluster ion beam (GCIB) or an ion implant beam containing the dopant gas.

2. The method of claim 1 , wherein the reactant gas comprises a silicon-containing gas selected from an alkyl silane, an alkoxysilane, an alkyl alkoxysilane, an alkyl siloxane, an alkoxysiloxane, an alkyl alkoxysiloxane, an aryl silane, an acyl silane, an aryl siloxane, an acyl siloxane, a silazane, or any combination thereof.

3. The method of claim 1 , wherein the modifying further comprises:

adsorbing the reactant gas on the metal surfaces; and

heat-treating the patterned substrate at a temperature that selectively removes the adsorbed reactant gas from the metal surfaces without removing the hydrophobic functional groups from the modified dielectric layer surfaces.

4. The method of claim 1 , further comprising:

exposing the metal surfaces to a reducing gas to reduce oxidized metal on the metal surfaces.

5. The method of claim 1 , further comprising:

following the exposing of the modified dielectric layer surfaces and the metal surfaces to the metal-containing precursor vapor and prior to the incorporating, removing the hydrophobic functional group from the modified dielectric layer surfaces.

6. The method of claim 1 , wherein the providing comprises:

providing a patterned substrate containing a dielectric layer having the dielectric layer surfaces, the patterned substrate further containing metal surfaces inside recessed features in the dielectric layer.

7. The method of claim 1 , wherein the metal surfaces are located on planarized metal layers filling recessed features in a dielectric layer.

8. A method of forming a semiconductor device, comprising:

providing a patterned substrate containing metal surfaces and dielectric layer surfaces;

modifying the dielectric layer surfaces by exposure to a reactant gas containing a hydrophobic functional group, the modifying substituting a hydrophilic functional group in the dielectric layer surfaces with the hydrophobic functional group; and

depositing metal-containing cap layers selectively on the metal surfaces by exposing the modified dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor and a non-metal dopant gas, wherein the modified dielectric layer surfaces and the metal surfaces are contemporaneously exposed to the metal-containing precursor vapor and the non-metal dopant gas, and wherein the metal-containing precursor vapor contains a metal element selected from platinum (Pt), gold (Au), ruthenium (Ru), cobalt (Co), tungsten (W), rhodium (Rh), iridium (Ir), or palladium (Pd), or a combination of two or more thereof, and the dopant gas is selected from PH 3 , BH 3 , B 2 H 6 , BF 3 , NF 3 , NH 3 , N 2 , N 2 H 4 , PF 3 , PBr 3 , BCl 3 , Bl 3 , SiH 4 , Si 2 H 6 , SiH 3 Cl, SiH 2 Cl 2 , SiHCl 3 , SiCl 4 , Si 2 Cl 6 , SiH 3 F, SiH 2 F, SiHF 3 , SiF 4 , Si 2 F 6 , GeH 4 , or GeCl 4 , or a combination of two or more thereof.

9. The method of claim 8 , wherein the metal-containing cap layers contain metal compound layers having the metal element and a non-metal dopant element selected from phosphorus (P), boron (B), nitrogen (N), fluorine (F), bromine (Br), silicon (Si), or germanium (Ge), or a combination of two or more thereof.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2009
From: ISHIZAKA, TADAHIRO; MIZUNO, SHIGERU; HOSHINO, SATOHIKO; NAGAI, HIROYUKI; CHIBA, YUKI; CERIO, FRANK M., JR.
To: TOKYO ELECTRON LIMITED
Reel/Frame 022476/0672 →
Continuity (1)
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