Apparatus, systems, and methods for low power computational imaging
The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.
1. A computing device to coordinate memory operations comprising:
memory fabric circuitry including a first memory slice and a second memory slice;
first processor circuitry in circuit with the first memory slice via a first bus;
second processor circuitry in circuit with the second memory slice via a second bus;
first power circuitry to provide a first supply voltage to the first processor circuitry;
second power circuitry to provide a second supply voltage to the second processor circuitry; and
first and second input registers in circuit with the first and second power circuitry, respectively, the first and second input registers to release input data from the memory fabric circuitry to one or more of the first or second processor circuitry in response to an indication that respective first or second power circuitry is ready.
2. The computing device as defined in claim 1 , further including a first tile in circuit with the first memory slice, the first tile including at least one port to communicate with the first processor circuitry.
3. The computing device as defined in claim 2 , wherein the first tile includes random access memory.
4. The computing device as defined in claim 2 , further including tile control circuitry to perform a data access request corresponding to a memory address of the memory fabric circuitry.
5. The computing device as defined in claim 4 , wherein the tile control circuitry is to provide a data access grant for the first memory slice in response to an indication the data access request does not include a clash.
6. The computing device as defined in claim 5 , wherein the tile control circuitry is to permit a direct memory access by the first memory slice to the memory address of the memory fabric circuitry when the indication that the data access request does not include the clash.
7. The computing device as defined in claim 1 , further including signal generator circuitry to generate an enable signal at an input of the first and second power circuitry.
8. The computing device as defined in claim 7 , wherein the signal generator circuitry is to cause the first and second input registers to release the input data in response to detecting the enable signal has propagated through the first and second power circuitry.
9. A system comprising:
memory fabric circuitry including a first memory slice and a second memory slice;
first processor circuitry communicatively connected with the first memory slice via first means for bus communication;
second processor circuitry communicatively connected with the second memory slice via second means for bus communication;
first means for power control to provide a first supply voltage to the first processor circuitry;
second means for power control to provide a second supply voltage to the second processor circuitry; and
first and second register means communicatively connected with the first and second power circuitry, respectively, the first and second register means to release input data from the memory fabric circuitry to one or more of the first or second processor circuitry in response to an indication that respective first means for power control or second means for power control is ready.
10. The system as defined in claim 9 , further including first tile means communicatively connected with the first memory slice, the first tile means including at least one means for port communication with the first processor circuitry.
11. The system as defined in claim 10 , wherein the first tile means includes random access memory (RAM).
12. The system as defined in claim 10 , further including means for tile control to perform a data access request corresponding to a memory address of the memory fabric circuitry.
13. The system as defined in claim 12 , wherein the means for tile control is to provide a data access grant for the first memory slice in response to an indication the data access request does not include a clash.
14. The system as defined in claim 13 , wherein the means for tile control is to permit a direct memory access by the first memory slice to the memory address of the memory fabric circuitry when the indication that the data access request does not include the clash.
15. The system as defined in claim 9 , further including means for signal generation to generate an enable signal at an input of the first and second means for power control.
16. The system as defined in claim 15 , wherein the means for signal generation is to cause the first and second register means to release the input data in response to detecting the enable signal has propagated through the first and second means for power control.
17. The computing device as defined in claim 1 , wherein the first processor circuitry includes a vector processor, and the second processor circuitry includes a hardware accelerator.
18. The system as defined in claim 9 , wherein one of the first processor circuitry or the second processor circuitry includes a vector processor, and an other one of the first processor circuitry or the second processor circuitry includes a hardware accelerator.