Methods for reducing disturb errors by refreshing data alongside programming or erase operations
A method is for ensuring data integrity in memory pages includes: dividing the memory pages into a predetermined number of refresh groups; and for each write operation to be performed on a selected memory page: (a) selecting one of the refresh groups; (b) reading data from the memory pages of the selected refresh group; and (d) concurrently (i) performing the write operation on the selected memory page, and (ii) writing back the data read into the memory pages of the selected refresh group.
1. A method ensuring data integrity in a plurality of memory pages, the memory pages being implemented in a 3-dimensional array of storage transistors, the method comprising:
dividing the memory pages into a predetermined number of refresh groups;
storing a value that represents a number of program or erase disturbs the memory pages have experienced, the value being stored in each of the memory pages;
and for each write operation to be performed on a selected one of the memory pages:
selecting one of the refresh groups;
reading data stored in storage transistors associated with the memory pages of the selected refresh group; and
concurrently (i) performing the write operation on the selected memory page, and (ii) writing the data read back into the storage transistors associated with the memory pages of the selected refresh group.
2. The method of claim 1 , wherein three or more copies of the value are stored in a designated one of the memory pages.
3. The method of claim 1 , further comprising (i) reading the value from both the selected page and one of the memory pages in the refresh group, and (ii) determining if the values read from the selected page and the memory page in the refresh group agree.
4. The method of claim 1 , wherein the refresh groups are selected one-by-one in a round-robin fashion.
5. The method of claim 1 , wherein the write operation comprises an erase phase and a program phase.
6. The method of claim 5 wherein, during the erase phase, the write operation carries out an erase operation on each storage transistor of the selected page that is designated to be set to the erased state.
7. The method of claim 5 wherein, during the program phase, the write operation carries an programming operation on each storage transistor in the selected page that is designated to be set to the programmed state.
8. The method of claim 1 , wherein (i) the value encodes one of a plurality of states representing an operating condition of the memory pages, (ii) each refresh group is selected for refresh in at least one of the states, and (iii) the value resets to an initial value after all the memory pages have been refreshed.
9. The method of claim 8 , wherein the operating condition relates to an inhibit scheme for non-selected storage transistors in the memory pages.
10. The method of claim 9 , wherein the value is represented in the memory pages as Grey codes.
11. The method of claim 1 , wherein the 3-dimensional array of storage transistors is organized as a 3-dimensional array of NOR memory strings, wherein each storage transistor is associated with one of a plurality of word lines and a common bit line that it shares with other storage transistors on its NOR memory string.
12. The method of claim 11 , wherein the predetermined number of refresh groups is determined from a figure of merit that represents a number of times voltages are applied to common bit lines associated with the storage transistors in non-selected memory pages during a write operation to inhibit the storage transistors from being written into.
13. The method of claim 11 , wherein the memory pages are organized as slices, each slice including a storage transistor from each memory page, the storage transistors of each slice being associated with the same word line and sharing a sense amplifier.
14. The method of claim 11 , wherein the concurrently (i) performing the write operation and (ii) writing back the data read comprises:
selecting one of word lines and one of the common bit lines;
biasing the selected word line and the selected common bit line to a predetermined voltage difference for a programming or erase operation;
biasing each of the non-selected common bit lines to a first voltage, such that, across the selected common bit line and each of the non-selected common bit line is imposed a first voltage difference that is a first fraction—less than 1.0 in magnitude—of the predetermined voltage difference; and
biasing each of the non-selected word lines to a second voltage, such that, across the selected common bit line and each of the non-selected common bit line, is imposed a second voltage difference that is a second fraction—less than 1.0 in magnitude—of the predetermined voltage difference.
15. The method of claim 14 , wherein the first voltage and the second inhibit voltage are approximately equal.
16. The method of claim 14 , wherein the first and second voltages have different values.
17. The method of claim 14 , wherein the first fraction is twice the second fraction.
18. The method of claim 14 , wherein the first fraction has a magnitude greater than 0.5.
19. The method of claim 14 , wherein the predetermined voltage difference is either 8.0 volts or −8.0 volts.
20. The method of claim 19 , wherein the second voltage difference has a magnitude between about 2.0 volts and about 6.0 volts.
21. The method of claim 19 , wherein the second voltage difference has a magnitude between about 1.0 volt and about 3.0 volts.
22. The method of claim 20 , wherein the first voltage difference has a magnitude between about 2.0 volts and about 6.0 volts.