Semiconductor memory device and manufacturing method thereof
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
1. A method of manufacturing a semiconductor memory device, the method comprising:
forming a base part;
sequentially forming, on the base part, a first etch stop layer, a source sacrificial layer, and a second etch stop layer;
forming a stack structure, including insulating patterns, on the second etch stop layer;
forming a channel structure that penetrates the stack structure, the second etch stop layer, the source sacrificial layer, and the first etch stop layer, wherein a portion of the channel structure is disposed in a portion of the base part;
forming a first trench that penetrates the stack structure and the second etch stop layer;
removing the source sacrificial layer; and
forming a source layer between the first and second etch stop layers.
2. The method of claim 1 , wherein a material of the insulating patterns has an etch selectivity with respect to a material of each of the first and second etch stop layers.
3. The method of claim 1 , wherein a material of the base part has an etch selectivity with respect to a material of each of the first and second etch stop layers.
4. The method of claim 1 , further comprising etching the channel structure,
wherein, while the channel structure is being etched, the first etch stop layer protects the base part from being etched.
5. The method of claim 1 , further comprising etching the channel structure,
wherein, while the channel structure is being etched, the second etch stop layer protects the insulating patterns from being etched.
6. The method of claim 1 , wherein the first and second etch stop layers include at least one of SiCO and SiCN.
7. The method of claim 1 , wherein the base part is a semiconductor substrate.
8. The method of claim 1 , wherein the base part includes a peripheral circuit device and an insulating layer that covers the peripheral circuit device.