Threshold voltage modulation for gate-all-around FET architecture

1. A method of forming a gate stack structure, the method comprising:

forming a dipole metal layer on a high-gate dielectric layer on a semiconductor structure formed on a substrate;

annealing the dipole metal layer; and

removing the dipole metal layer, wherein

the dipole metal layer comprises dopants in the high-K gate dielectric layer.

2. The method of claim 1 , wherein the forming of the dipole metal layer comprises:

blanket depositing the dipole metal layer on the semiconductor structure; and

patterning the dipole metal layer.

3. The method of claim 1 , wherein

the high-K gate dielectric layer comprises hafnium oxide (HfO 2 ).

4. The method of claim 3 , wherein

the dipole metal layer comprises lanthanum (La).

5. The method of claim 3 , wherein

the dipole metal layer comprises aluminum (Al).

6. The method of claim 3 , wherein

the dipole metal layer comprises niobium (Nb).

7. The method of claim 1 , wherein

the dipole metal layer has a thickness of between 3 Å and 20 Å.

8. A method of forming a gate stack structure, the method comprising:

forming a p-type work function adjusting layer on a high-k gate dielectric layer on a semiconductor structure formed on a substrate;

forming an n-type work function adjusting layer on the high-K gate dielectric layer; and

forming a metal gate electrode on the p-type work function adjusting layer and the n-type work function adjusting layer, wherein

the p-type work function adjusting layer comprises p-doped conductive material, and

the n-type work function adjusting layer comprises n-doped conductive material.

9. The method of claim 8 , wherein

the metal gate electrode comprises tungsten (W).

10. The method of claim 8 , wherein

the p-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

11. The method of claim 8 , wherein

the n-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

12. A method of forming a gate stack structure on a semiconductor structure, the method comprising:

forming an interfacial layer on a semiconductor structure;

forming a high-K gate dielectric layer on the interfacial layer;

forming a dipole metal layer comprising dopants in the high-gate dielectric layer on the high-K gate dielectric layer;

annealing the dipole metal layer;

removing the dipole metal layer;

forming a first high-K dielectric cap layer on the high-K gate dielectric layer;

forming a p-type work function adjusting layer on the high-K gate dielectric layer;

forming an n-type work function adjusting layer on the high-K gate dielectric layer;

forming a second high-K dielectric cap layer on the p-type work function adjusting layer and the n-type work function adjusting layer; and

forming a metal gate electrode on the second high-K dielectric cap layer, wherein

the p-type work function adjusting layer comprises p-doped conductive material, and

the n-type work function adjusting layer comprises n-doped conductive material.

13. The method of claim 12 , wherein the forming of the dipole metal layer comprises:

blanket depositing the dipole metal layer on the high-K gate dielectric layer; and

patterning the dipole metal layer.

14. The method of claim 12 , wherein

the high-K gate dielectric layer comprises hafnium oxide (HfO 2 ).

15. The method of claim 14 , wherein

the dipole metal layer comprises lanthanum (La).

16. The method of claim 14 , wherein

the dipole metal layer comprises aluminum (Al) or niobium (Nb).

17. The method of claim 12 , wherein

the metal gate electrode comprises tungsten (W).

18. The method of claim 17 , wherein

the p-type work function adjusting layer has a thickness of between 5 Å and 30 Å.

19. The method of claim 17 , wherein

the n-type work function adjusting layer comprises n-doped conductive material and has a thickness of between 35 Å and 30 Å.

20. The method of claim 12 , wherein

the first high-K dielectric cap layer and the second high-K dielectric cap layer each comprise titanium nitride (TIN).