Semiconductor device

1. A semiconductor device comprising:

a substrate;

a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and

a first diode connected between the signal line and a first wiring,

wherein the first wiring is one of the power supply wiring and the ground wiring,

wherein the first diode includes

a first impurity region of a first conductive type, electrically connected to the signal line, and

a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring, and

wherein the signal line, the first wiring, or both is formed in the substrate.

2. The semiconductor device according to claim 1 further comprising:

a second diode connected between the signal line and a second wiring,

wherein the second wiring is the other of the power supply wiring and the ground wiring,

wherein the second diode includes

a third impurity region of the second conductive type, electrically connected to the signal line, and

a fourth impurity region of the first conductive type, electrically connected to the second wiring,

wherein the signal line, the second wiring, or both is formed in the substrate.

3. The semiconductor device according to claim 2 ,

wherein the signal line is formed in the substrate,

wherein a portion of the signal line connected to the first impurity region and a portion of the signal line connected to the third impurity region are connected to each other.

4. The semiconductor device according to claim 2 ,

wherein the first wiring and the second wiring are formed in the substrate.

5. The semiconductor device according to claim 2 ,

wherein the first diode includes a fifth impurity region of the second conductive type, formed in the substrate,

wherein the second diode includes a sixth impurity region of the first conductive type, formed in the substrate,

wherein the first impurity region and the second impurity region are arranged separated from each other on the fifth impurity region, and

wherein the third impurity region and the fourth impurity region are arranged separated from each other on the sixth impurity region.

6. The semiconductor device according to claim 5 ,

wherein in a plan view, the signal line, the first wiring, or both formed in the substrate extends in a direction parallel to a direction in which the first impurity region and the second impurity region are aligned, and

wherein in a plan view, the signal line, the second wiring, or both formed in the substrate extends in a direction parallel to a direction in which the third impurity region and the fourth impurity region are aligned.

7. The semiconductor device according to claim 5 ,

wherein in a plan view, the signal line, the first wiring, or both formed in the substrate extends in a direction different from a direction in which the first impurity region and the second impurity region are aligned, and

wherein in a plan view, the signal line, the second wiring, or both formed in the substrate extends in a direction different from a direction in which the third impurity region and the fourth impurity region are aligned.

8. The semiconductor device according to claim 2 ,

wherein the first impurity region and the second impurity region are arranged adjacent to each other on the substrate, and

wherein the third impurity region and the fourth impurity region are arranged adjacent to each other on the substrate.

9. The semiconductor device according to claim 8 ,

wherein in a plan view, the signal line, the first wiring, or both formed in the substrate extends in a direction parallel to a direction in which the first impurity region and the second impurity region are aligned, and

wherein in a plan view, the signal line, the second wiring, or both formed in the substrate extends in a direction parallel to a direction in which the third impurity region and the fourth impurity region are aligned.

10. The semiconductor device according to claim 8 ,

wherein in a plan view, the signal line, the first wiring, or both formed in the substrate extends in a direction different from a direction in which the first impurity region and the second impurity region are aligned, and

wherein in a plan view, the signal line, the second wiring, or both formed in the substrate extends in a direction different from a direction in which the third impurity region and the fourth impurity region are aligned.

11. The semiconductor device according to claim 2 ,

wherein the first impurity region, the second impurity region, the third impurity region, and the fourth impurity region are formed in any of a plurality of fins formed on the substrate.

12. The semiconductor device according to claim 11 ,

wherein a number of first fins, of the plurality of fins, connected to the signal line, the first wiring, or both formed in the substrate is less than a number of second fins adjacent to the first fins, and

wherein a number of third fins, of the plurality of fins, connected to the signal line, the second wiring, or both formed in the substrate is less than a number of fourth fins adjacent to the third fins.

13. The semiconductor device according to claim 2 further comprising:

a first guard ring portion surrounding the first diode in a plan view; and

a second guard ring portion surrounding the second diode in a plan view.

14. The semiconductor device according to claim 13 ,

wherein a power supply potential is supplied to the first wiring formed in the substrate from above the first guard ring portion, and

wherein a power supply potential is supplied to the second wiring formed in the substrate from above the second guard ring portion.

15. The semiconductor device according to claim 13 ,

wherein a power supply potential is supplied to the first wiring formed in the substrate from outside the first guard ring portion in a plan view, and

wherein a power supply potential is supplied to the second wiring formed in the substrate from outside the second guard ring portion in a plan view.

16. The semiconductor device according to claim 2 ,

wherein a power supply potential is supplied to the first wiring formed in the substrate from a rear surface of the substrate, and

wherein a power supply potential is supplied to the second wiring formed in the substrate from the rear surface of the substrate.

17. The semiconductor device according to claim 2 further comprising:

a dummy-wiring formed in the substrate, insulated from the signal line, the first wiring, or both formed in the substrate, and insulated from the signal line, the second wiring, or both formed in the substrate.