Method for preparing semiconductor device with composite dielectric structure
The present disclosure provides a method for preparing a semiconductor device with a composite dielectric structure. The method includes forming a photoresist pattern structure over a first semiconductor die. The method also includes forming a second dielectric layer surrounding the photoresist pattern structure, and removing the photoresist pattern structure to form a first opening in the second dielectric layer. The method further includes forming dielectric spacers along sidewalls of the first opening, and forming an interconnect structure surrounded by the dielectric spacers. In addition, the method includes bonding a second semiconductor die to the second dielectric layer. The second semiconductor die includes a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.
1. A method for preparing a semiconductor device, comprising:
forming a photoresist pattern structure over a first semiconductor die, wherein the first semiconductor die comprises a first dielectric layer and a first conductive pad embedded in the first dielectric layer, and the first conductive pad is covered by the photoresist pattern structure;
forming a second dielectric layer surrounding the photoresist pattern structure;
removing the photoresist pattern structure to form a first opening in the second dielectric layer;
forming dielectric spacers along sidewalls of the first opening;
forming an interconnect structure surrounded by the dielectric spacers; and
bonding a second semiconductor die to the second dielectric layer, wherein the second semiconductor die comprises a second conductive pad facing the interconnect structure, and the second conductive pad is electrically connected to the first conductive pad of the first semiconductor die through the interconnect structure.
2. The method for preparing a semiconductor device of claim 1 , wherein the photoresist pattern structure comprises a first portion and a second portion, the first portion of the photoresist pattern structure is removed to form the first opening in the second dielectric layer, the second portion of the photoresist pattern structure is removed to form a second opening in the second dielectric layer, and a width of the first opening is greater than a width of the second opening.
3. The method for preparing a semiconductor device of claim 2 , further comprising:
depositing a third dielectric layer over the second dielectric layer after the photoresist pattern structure is removed, wherein the first opening is partially filled by the third dielectric layer while the second opening is entirely filled by the third dielectric layer.
4. The method for preparing a semiconductor device of claim 3 , further comprising:
performing a first dry etching process on the third dielectric layer such that the dielectric spacers are formed in the first opening, and the second opening is filled by a dielectric structure, wherein the dielectric structure is wider than each of the dielectric spacers.
5. The method for preparing a semiconductor device of claim 1 , further comprising:
forming a dielectric lining layer over the first dielectric layer before the photoresist pattern structure is formed, wherein the first conductive pad is covered by the dielectric lining layer.
6. The method for preparing a semiconductor device of claim 5 , further comprising:
performing a second dry etching process on the dielectric lining layer using the dielectric spacers as a mask, such that the first conductive pad is exposed in the first opening before the interconnect structure is formed.
7. The method for preparing a semiconductor device of claim 1 , wherein the step of forming the interconnect structure comprises:
forming a conductive lining layer over the second dielectric layer, the dielectric spacers and the first conductive pad;
forming a conductive layer over the conductive lining layer; and
polishing the conductive lining layer and the conductive layer to expose the second dielectric layer and the dielectric spacers.