Timing path analysis using flow graphs
A method for timing path analysis using flow graphs. The method includes receiving timing data associated with an integrated circuit (IC) design. The timing data includes a plurality of timing paths. The method also includes generating a graphical representation of the plurality of timing paths. A timing path is represented as a flow ribbon across one or more components of the IC design. A display attribute of the flow ribbon is indicative of a metric of the timing path. The graphical representation is provided in a graphical user interface (GUI) to a user.
1. A method comprising:
receiving timing data associated with an integrated circuit (IC) design, wherein the timing data includes a plurality of timing paths;
generating, by a processor, a graphical representation of the plurality of timing paths as a plurality of corresponding flow ribbons, wherein a timing path of the plurality of timing paths is represented as a flow ribbon of the plurality of corresponding flow ribbons across one or more components of the IC design and wherein a display attribute of the flow ribbon is indicative of a metric of the timing path; and
providing the graphical representation in a graphical user interface (GUI) to a user.
2. The method of claim 1 , further comprising:
configuring a width of the flow ribbon based on a number of connections in the timing path.
3. The method of claim 1 , wherein the metric includes a worst negative slack, a total negative slack, or a number of violating paths.
4. The method of claim 1 , wherein a first dimension of the graphical representation corresponds to a connection level, and wherein generating the graphical representation of the timing data further comprises:
arranging a component of the IC design in the first dimension of the graphical representation based on a location of the component in the timing path.
5. The method of claim 1 , wherein generating the graphical representation of the plurality of timing paths further comprises:
assigning a first value corresponding to a connection level in the timing path to a component of the IC design;
representing the component of the IC design in a second dimension in the graphical representation;
aligning the component to associated connected components in the timing path; and
repositioning the component in the second dimension to remove one or more overlaps in a representation of the components.
6. The method of claim 5 , further comprising:
repeating the aligning and the repositioning for each connection level in a first dimension.
7. The method of claim 1 , further comprising:
modifying a display attribute associated with a component of the one or more components in response to a user input.
8. The method of claim 1 , further comprising:
generating additional graphical representation in response to a user selecting a component in the graphical representation, wherein the additional graphical representation includes an input connection and an output connection of the selected component.
9. The method of claim 8 , wherein generating the additional graphical representation comprises:
identifying one or more timing paths associated with the selected component;
displaying the identified timing paths as ribbon flows in the additional graphical representation; and
providing the additional graphical representation in another GUI to the user.
10. The method of claim 9 , further comprising:
reordering the one or more ribbon flows in a second dimension of the additional graphical representation to remove overlaps between components.
11. A system comprising:
a memory storing instructions; and
a processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:
receive timing data associated with an integrated circuit (IC) design, wherein the timing data includes a plurality of timing paths;
generate a graphical representation of the plurality of timing paths as a plurality of corresponding graphical objects, wherein a timing path of the plurality of timing paths is represented as a graphical object of the plurality of corresponding graphical objects across one or more components of the IC design and wherein a display attribute of the graphical object is indicative of a metric of the assign a first value corresponding to a connection level in the timing path to a component of the IC design;
represent the component of the IC design in a second dimension in the graphical representation;
align the component to associated connected components in the timing path;
reposition the component in the second dimension to remove one or more overlaps in a representation of the components; and
provide the graphical representation in a graphical user interface (GUI) to a user.
12. The system of claim 11 , wherein the processor is further configured to:
configure a width of the graphical object based on a number of connections in the timing path.
13. The system of claim 11 , wherein the metric includes a worst negative slack, a total negative slack, or a number of violating paths.
14. The system of claim 11 , wherein a first dimension of the graphical representation corresponds to a connection level, and wherein the processor is further configured to:
arrange a component of the IC design in the first dimension of the graphical representation based on a location of the component in the timing path.
15. The system of claim 11 , wherein the processor is further configured to:
repeat the aligning and the repositioning for each connection level in a first dimension.
16. The system of claim 11 , wherein the processor is further configured to:
modify a display attribute associated with a component of the one or more components in response to a user input.
17. The system of claim 11 , wherein the processor is further configured to:
generate an additional graphical representation in response to a user selecting a component in the graphical representation, wherein the additional graphical representation includes an input connection and an output connection of the selected component.
18. The system of claim 17 , wherein the processor is further configured to:
identify one or more timing paths associated with the selected component; displaying the identified timing paths as graphical objects in the additional graphical representation; and
provide the additional graphical representation in another GUI to the user.
19. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
receive timing data associated with an integrated circuit (IC) design, wherein the timing data includes a plurality of timing paths;
generate a graphical representation of the plurality of timing paths as a plurality of corresponding flow ribbons, wherein a timing path of the plurality of timing paths is represented as a flow ribbon of the plurality of corresponding flow ribbons across one or more components of the IC design and wherein a display attribute of the flow ribbon is indicative of a metric of the timing path; and
provide the graphical representation in a graphical user interface (GUI) to a user.