Memory device defect scanning
A method includes determining that a criteria involving a memory device is met and performing a defect scan involving memory dice of the memory device in response to the criteria being met. The method further includes determining, as part of performing the defect scan, whether at least one memory die of the memory device has experienced degradation. The defect scan is performed as part of a quality and reliability assurance test or a reliability demonstration test, or both.
1. A method, comprising:
receiving a memory access command from a host and determining that a criteria involving a memory device is met, wherein the criteria includes a number of program-erase cycles (PECs) for at least one memory die of a number of memory dice of the memory device is above a threshold quantity;
performing a defect scan involving the number of memory dice of the memory device in response to receiving the memory access command and the criteria being met by scanning each of the number of memory dice on an entire die-by-entire die basis;
determining, as part of performing the defect scan, whether at least one memory die of the memory device has experienced degradation; and
responsive to determining that the at least one memory die has experienced degradation, refraining from fulfilling the memory access command to read data written to the at least one memory die that has experienced the degradation, performing a recovery operation for user data on the at least one memory die requested by the memory access command, and transfer the recovered user data to the host to fulfill the memory access command.
2. The method of claim 1 , wherein determining that the criteria is met includes determining that the memory device has been in operation for a threshold period of time.
3. The method of claim 1 , wherein the degradation of each memory die is evaluated through test data including: bit flips, drift effects and uncorrectable errors.
4. The method of claim 1 , wherein performing the defect scan includes analyzing each of the number of memory dice independently to determine whether the at least one memory die of the memory device has experienced the degradation.
5. The method of claim 1 , further comprising performing the defect scan as part of performing a quality and reliability test involving the number of memory dice during idle time of the memory device or during idle time of a host couplable to the memory device, or both.
6. The method of claim 1 , further comprising performing the defect scan involving the number of memory dice in the absence of a host couplable to the memory device detecting a write failure or a read failure involving the at least one memory die.
7. The method of claim 1 , further comprising:
writing, as part of performing the defect scan, test data to the number of memory dice of the memory device;
reading, after a threshold period of time has elapsed, the test data from the number of memory dice of the memory device; and
comparing the test data read from the number of memory dice to the test data written to the number of memory dice to determine whether the at least one memory die of the memory device has experienced degradation.
8. An apparatus, comprising:
a memory device comprising a plurality of memory dice; and
a controller couplable to the memory device, wherein the controller is configured to:
receive a memory access command from a host and determine that a criteria involving the plurality of memory dice is met, wherein the criteria includes a number of program-erase cycles (PECs) for at least one memory die of the plurality of memory dice of the memory device is above a threshold quantity;
write test data to the at least one memory die in response to the determination that the criteria is met;
read, after a threshold period of time has elapsed, the test data from the at least one memory die; and
compare the test data read from the at least one memory die to the test data written to the at least one memory die to determine whether the at least one memory die has experienced degradation; and
responsive to determine at the at least one memory die has experienced degradation, refraining from fulfilling the memory access command to read data written to the at least one memory die that has experienced the degradation, performing a recovery operation for user data on the at least one memory die requested by the memory access command, and transfer the recovered user data to a host to fulfill the memory access command.
9. The apparatus of claim 8 , wherein the controller is further configured to determine that the memory device has been in operation for a threshold period of time to determine that the criteria is met.
10. The apparatus of claim 8 , wherein the degradation of each memory die is evaluated through test data including: bit flips, drift effects and uncorrectable errors.
11. The apparatus of claim 8 , wherein the controller is further configured to write the test data, read the test data, and compare the test data read from the at least one memory die to the test data written to the at least one memory die in the absence of a host couplable to the memory device detecting a write failure or a read failure involving the at least one memory die.
12. The apparatus of claim 8 , wherein the controller is further configured to write the test data, read the test data, and compare the test data read from the at least one memory die to the test data written to the at least one memory die as part of performance of a quality and reliability test or a reliability demonstration test, or both.
13. The apparatus of claim 8 , wherein the controller is further configured to write the test data, read the test data, and compare the test data read from the at least one memory die to the test data written to the at least one memory die during runtime of the memory device.
14. The apparatus of claim 8 , wherein the controller is further configured to:
write the test data to each memory die of the plurality of memory dice independently of one another;
read the test data from each memory die of the plurality of memory dice independently of one another; and
compare the test data read from each respective memory die to the test data written to each of the respective memory die independently of one another.
15. The apparatus of claim 8 , wherein the memory device comprises a NAND memory device or a three-dimensional crosspoint memory device.
16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a memory access command from a host and determine that a criteria involving a memory device is met, wherein the criteria includes a number of program-erase cycles (PECs) for at least one memory die of a number of memory dice of the memory device is above a threshold quantity;
determine that the memory device has been in operation for a first threshold period of time;
write test data to each memory die of the number of memory dice in response to the determination that the memory device has been in operation for the first threshold period of time;
read, after a second threshold period of time has elapsed, the test data from each memory die of the number of memory dice; and
compare the test data read from respective memory dice of the number of memory dice to the test data written to respective memory dice of the number of memory dice to determine whether at least one memory die of the number of memory dice has experienced a defect or degradation, or both; and
responsive to a determination that the at least one memory die has experienced degradation, refraining from fulfilling the memory access command to read data written to the at least one memory die that has experienced the degradation, performing a recovery operation for user data on the at least one memory die requested by the memory access command, and transfer the recovered user data to a host to fulfill the memory access command.
17. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to write the test data, read the test data, and compare the test read from respective memory dice of the number of memory dice to the test data written to respective memory dice of the number of memory dice for each memory die of the number of memory dice independently from one another.
18. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to write the test data, read the test data, and compare the test read from respective memory dice of the number of memory dice to the test data written to respective memory dice of the number of memory dice for each memory die of the number of memory dice during performance of a background media management operation during idle time of the memory device or during idle time of a host couplable to the memory device, or both.
19. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to write the test data, read the test data, and compare the test read from respective memory dice of the number of memory dice to the test data written to respective memory dice of the number of memory dice for each memory die of the number of memory dice in the absence of a host couplable to the memory device detecting a write failure or a read failure involving at least one of the number of memory dice.
20. The non-transitory computer-readable storage medium of claim 16 , wherein the processing device is further to write the test data, read the test data, and compare the test read from respective memory dice of the number of memory dice to the test data written to respective memory dice of the number of memory dice for each memory die of the number of memory dice in the absence of a host couplable to the memory device detecting an uncorrectable error involving host data read from at least one of the number of memory dice.