Coding and modulation method, demodulation and decoding method, apparatus, and device

1. A coding and modulating method implemented by a coding and modulating apparatus in a communication system, comprising:

obtaining, by the coding and modulating apparatus, K to-be-encoded bits and a modulation scheme, wherein K is an integer greater than or equal to 1;

encoding, by the coding and modulating apparatus, the K to-be-encoded bits, based on M bit levels of the modulation scheme, to obtain M′ code blocks, wherein M′<M, a code length of an i th code block is N i , and N i =M i *N, wherein M i is a quantity of bit levels corresponding to the i th code block, N is a symbol block length, i is an integer from 1 to M′, and Σ i=1 i=M′ (M i )=M, and wherein a quantity of information bits comprised in the i th code block is K i , Σ i=1 i=M′ (K i )=K, and M, M′, N, N i , M i , and K i are all positive integers;

modulating, by the coding and modulating apparatus, the M′ code blocks, according to a mapping relationship between the code blocks and the M bit levels, to obtain a modulated symbol sequence, wherein a code block having a code length of M i *N corresponds to M i bit levels in the mapping relationship; and

sending, by the coding and modulating apparatus, the modulated symbol sequence to a receiving device in the communication system via a communication channel between the coding and modulating apparatus and the receiving device.

2. The method according to claim 1 , wherein at least two of the M′ code blocks have different code lengths.

3. The method according to claim 1 , wherein an absolute value of a bit-level capacity difference between the M, bit levels to which the code block having the code length of M i *N is mapped is less than or equal to a preset difference.

4. The method according to claim 1 , wherein the encoding the K to-be-encoded bits based on the M bit levels of the modulation scheme comprises:

classifying the K to-be-encoded bits into M′ to-be-encoded sequences based on bit-level capacities of the M bit levels; and

separately encoding the M′ to-be-encoded sequences to obtain the M′ code blocks.

5. The method according to claim 4 , wherein the classifying the K to-be-encoded bits into the M′ to-be-encoded sequences based on the bit-level capacities of the M bit levels comprises:

classifying the M bit levels into M′ groups of bit levels, wherein each group of bit levels comprises at least one bit level; and

classifying the K to-be-encoded bits into the M′ to-be-encoded sequences based on N, a quantity of bit levels comprised in each group of bit levels, and a bit-level capacity of each bit level in each group of bit levels.

6. The method according to claim 1 , wherein the modulating the M′ code blocks according to the mapping relationship between the M′ code blocks and the M bit levels comprises:

for any i th code block, when M, is equal to 1, mapping the i th code block to an i th group of bit levels in a constellation diagram; and

for any i th code block, when M, is greater than 1, converting the i th code block into M, bit streams, and separately mapping the M, bit streams to the i th group of bit levels in the constellation diagram, wherein a length of each bit stream is N, and one bit stream is mapped to one bit level of the i th group of bit levels.

7. The method according to claim 6 , wherein a difference between bit-level capacities of bit levels in the i th group of bit levels is less than or equal to a preset difference.

8. The method according to claim 6 , wherein before the converting the i th code block into the M i bit streams, the method further comprises:

performing interleaving processing on the i th code block.

9. The method according to claim 1 , wherein when the modulation scheme is 8-phase shift keying (PSK) modulation or 8-differential phase shift keying (DPSK) modulation, M=3, M′=2, a code length of one code block is N, and a code length of another code block is 2N.

10. The method according to claim 1 , wherein when the modulation scheme is 16 quadrature amplitude modulation (QAM), M=4, M′=3, a code length of two code blocks is N, and a code length of another code block is 2N.

11. A coding and modulation apparatus, comprising:

at least one non-transitory memory, configured to store program instructions;

an input interface configured to obtain K to-be-encoded bits and a modulation scheme, wherein K is an integer greater than or equal to 1;

at least one processor coupled to the receiver and the at least one non-transitory memory, wherein when executing the program instructions, the at least one processor is configured to:

encode the K to-be-encoded bits based on M bit levels of the modulation scheme, to obtain M′ code blocks, wherein M′<M, a code length of an i th code block is N i , and N i =M i *N, wherein M i is a quantity of bit levels corresponding to the i th code block, N is a symbol block length, i is an integer from 1 to M′, and Σ i=1 i=M′ (M i )=M, and wherein a quantity of information bits comprised in the i th code block is K i , Σ i=1 i=M′ (K i )=K, and M, M′, N, N i , M i , and K i are all positive integers; and

modulate the M′ code blocks according to a mapping relationship between the M′ code blocks and the M bit levels, to obtain a modulated symbol sequence, wherein a code block having a code length of M i *N corresponds to M i bit levels in the mapping relationship; and

an output interface coupled to the at least one processor and configured to output the modulated symbol sequence.

12. The apparatus according to claim 11 , wherein at least two of the M′ code blocks have different code lengths.

13. The apparatus according to claim 11 , wherein an absolute value of a bit-level capacity difference between the M i bit levels to which the code block having the code length of M i *N is mapped is less than or equal to a preset difference.

14. The apparatus according to claim 11 , wherein the at least one processor is further configured to:

classify the K to-be-encoded bits into M′ to-be-encoded sequences based on bit-level capacities of the M bit levels; and

separately encode the M′ to-be-encoded sequences to obtain the M′ code blocks.

15. The apparatus according to claim 14 , wherein the at least one processor is further configured to:

classify the M bit levels into M′ groups of bit levels, wherein each group of bit levels comprises at least one bit level; and

classify the K to-be-encoded bits into the M′ to-be-encoded sequences based on N, a quantity of bit levels comprised in each group of bit levels, and a bit-level capacity of each bit level in each group of bit levels.

16. The apparatus according to claim 11 , wherein the at least one processor is further configured to:

for any i th code block, when M, is equal to 1, map the i th code block to an i th group of bit levels in a constellation diagram; and

for any i th code block, when M, is greater than 1, convert the i th code block into M, bit streams, and separately map the M, bit streams to the i th group of bit levels in the constellation diagram, wherein a length of each bit stream is N; and one bit stream is mapped to one bit level of the i th group of bit levels.

17. The apparatus according to claim 16 , wherein a difference between bit-level capacities of bit levels in the i th group of bit levels is less than or equal to a preset difference.

18. The apparatus according to claim 16 , wherein the at least one processor is further configured to: before the modulation module converts the i th code block into the M, bit streams, perform interleaving processing on the i th code block.

19. A demodulating and decoding apparatus, comprising:

at least one non-transitory memory, configured to store program instructions;

an input interface configured to

obtain N modulated symbols corresponding to M′ code blocks, wherein M′<M, M is a quantity of bit levels of a modulation scheme, N is a symbol block length, a code length of an i th code block is N i , N=M i *N, M i is a quantity of bit levels corresponding to the i th code block, i is an integer from 1 to M′, Σ i=1 i=M′ (M i )=M, and M, M′, N, N i , and M i are all positive integers; and

at least one processor coupled to the at least one non-transitory memory and the receiver, wherein when executing the program instructions, the at least one processor is configured to:

sequentially demodulate and decode the M′ code blocks based on the N modulated symbols, to obtain decoding results of the M′ code blocks.

20. The apparatus according to claim 19 , wherein the at least one processor is further configured to:

perform demodulation processing on the i th code block, wherein the demodulation processing comprises adding 1 to i, and determining an LLR of the i th code block based on decoding results of first (i−1) code blocks and the N modulated symbols, and wherein an initial value of i is 0;

perform decoding processing on the i th code block, wherein the decoding processing comprises determining a decoding result of the i th code block based on the LLR of the i th code block; and

repeatedly perform the demodulation processing and the decoding processing until the decoding results of the M′ code blocks are obtained.