Lithium niobate or lithium tantalate FBAR structure and fabricating method thereof
A method for fabricating a film bulk acoustic resonator (FBAR) structure includes: obtaining a wafer, at least a portion of the wafer is made of a piezoelectric material; forming a bottom electrode layer on the wafer; patterning the bottom electrode layer to form a bottom electrode; forming a sacrificial island on the bottom electrode; bonding a bottom cap wafer onto the bottom electrode; processing the wafer to form a piezoelectric layer; forming a top electrode layer on the piezoelectric layer; patterning the top electrode layer to form a top electrode; and removing the sacrificial island to form a cavity.
1. A method for fabricating a film bulk acoustic resonator (FBAR) structure, comprising:
obtaining a wafer, wherein at least a portion of the wafer is made of a piezoelectric material;
forming a bottom electrode layer on the wafer;
patterning the bottom electrode layer to form a bottom electrode;
forming a sacrificial island on the bottom electrode, wherein the bottom electrode includes a first surface facing the wafer, a second surface opposite to the first surface, and a side surface between the first surface and the second surface, and the sacrificial island directly contacts the side surface of the bottom electrode;
forming a boundary layer covering, and being in conformance with, the sacrificial island;
forming a bottom bonding layer on the boundary layer;
bonding a bottom cap wafer onto the bottom bonding layer;
processing the wafer to form a piezoelectric layer;
forming a top electrode layer on the piezoelectric layer;
patterning the top electrode layer to form a top electrode; and
removing the sacrificial island to form a cavity, wherein the cavity exposes the side surface of the bottom electrode.
2. The method of claim 1 , wherein the wafer includes a first substrate, a silicon oxide layer, and a piezoelectric layer sequentially stacked together.
3. The method of claim 2 , wherein the processing the wafer includes:
removing the first substrate and the silicon oxide layer to expose the piezoelectric layer.
4. The method of claim 1 , wherein the wafer is formed of a lithium niobate (LiNbO 3 ) or lithium tantalate (LiTaO 3 ) material, and
the processing the wafer includes thinning the wafer to form the piezoelectric layer.
5. The method of claim 1 , wherein the piezoelectric material is lithium niobate (LiNbO 3 ) or lithium tantalate (LiTaO 3 ).
6. The method of claim 1 , further comprising:
forming a raised structure along an edge of the top electrode.
7. The method of claim 1 , further comprising:
forming a raised structure along an edge of the bottom electrode, the raised structure protruding towards the cavity.
8. The method of claim 1 , further comprising:
before patterning the bottom electrode layer, forming a bottom passivation layer on the bottom electrode layer.
9. The method of claim 1 , further comprising:
before patterning the top electrode layer, forming a top passivation layer on the top electrode layer.
10. The method of claim 9 , further comprising:
after patterning the top electrode layer to form the top electrode, patterning the top passivation layer to form a top electrode contact window; and
patterning the piezoelectric layer to form a bottom electrode contact window.
11. The method of claim 10 , further comprising:
forming a top electrode contact layer that electrically connects to the top electrode via the top electrode contact window; and
forming a bottom electrode contact layer that electrically connects to the bottom electrode via the bottom electrode contact window.
12. The method of claim 1 , wherein the bottom cap wafer is made of silicon, glass or sapphire.
13. The method of claim 1 , wherein a vertical projection of an edge of the top electrode is located within the cavity.
14. The method of claim 1 , wherein a vertical projection of an edge of the bottom electrode is located within the cavity.
15. The method of claim 1 , wherein the top electrode and the bottom electrode are made of molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), or a stacked combination of two or more of those materials.
16. The method of claim 1 , wherein the processing the wafer is performed by a grinding process, a plasma dry etching process, a wet chemical etching process, or a combination thereof.
17. The method of claim 1 , wherein the forming the sacrificial island on the bottom electrode comprises:
forming a sacrificial layer on the bottom electrode; and
patterning the sacrificial layer to form the sacrificial island.
18. The method of claim 17 , wherein the sacrificial layer includes at least one of pure silicon oxide, phosphor silicate glass (PSG), boron phosphor silicate glass (BPSG), spin on glass (SOG), or fluorinated silicate glass (FSG).
19. The method of claim 1 , wherein the removing the sacrificial island is performed by hydrofluoric acid solution wet etching, buffered oxide etchant (BOE) solution wet etching, hydrofluoric acid vapor corrosion, or a combination of two or more of those processes.