ESD protection device with isolation structure layout that minimizes harmonic distortion
An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.
1. An ESD protection device, comprising:
a semiconductor body comprising an upper surface;
a plurality of p-type wells that each extend from the upper surface into the semiconductor body;
a plurality of n-type wells that each extend from the upper surface into the semiconductor body;
first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body; and
second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body,
wherein the p-type wells and the n-type wells alternate with one another in a first direction, and
wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.
2. The ESD protection device of claim 1 , wherein each of the p-type wells and the n-type wells are spaced apart from one another in the first direction, wherein each of the p-type wells and the n-type wells have an elongated rectangle geometry, and wherein elongated sides of the p-type wells and the n-type wells run parallel to a second direction that is perpendicular to the first direction.
3. The ESD protection device of claim 2 , wherein the first isolation regions comprise first and second elongated sections that adjoin both of the elongated sides of the p-type wells, wherein the second isolation regions comprise first and second elongated sections that adjoin both of the elongated sides of the n-type wells, and wherein a total width of the first and second elongated sections of the first isolation regions is greater than a total width of the first and second elongated sections of the second isolation regions.
4. The ESD protection device of claim 2 , wherein the first isolation regions comprise first and second shortened sections that adjoin both end sides of the p-type wells, wherein the second isolation regions comprise first and second shortened sections that adjoin both end sides of the n-type wells, and wherein a total width of the first and second shortened sections of the first isolation regions is greater than a total width of the first and second shortened sections of the second isolation regions.
5. The ESD protection device of claim 1 , wherein the first isolation regions are provided by a plurality of separate dielectric regions in the semiconductor body each having an outer boundary that surrounds one of the p-type wells, and wherein the second isolation regions are provided by a plurality of separate dielectric regions in the semiconductor body each having an outer boundary that surrounds one of the n-type wells.
6. The ESD protection device of claim 1 , wherein the first isolation regions are provided by a continuous dielectric region in the semiconductor body that surrounds multiple ones of the p-type wells, and wherein the second isolation regions are provided by a plurality of separate dielectric regions in the semiconductor body each having an outer boundary that surrounds one of the n-type wells.
7. The ESD protection device of claim 1 , wherein the isolating area of the first isolation region is at least 10% greater than the isolating area of the second isolation regions.
8. The ESD protection device of claim 1 , wherein the first isolation regions and the second isolation regions are each defined by a trench formed in the upper surface, and wherein the trenches that define the first isolation regions and the second isolation regions are filled with at least one of: a dielectric material, a gas, and a vacuum.
9. The ESD protection device of claim 1 , wherein each of the n-type wells comprise first and second shallow doped zones that form a p-n junction with one another and have a higher dopant concentration as subjacent regions of the n-type wells, wherein each of the p-type wells comprise third and fourth shallow doped zones that form a p-n junction with one another and have a higher dopant concentration as subjacent regions of the p-type wells, and wherein the ESD protection device is configured as a silicon controlled rectifier.
10. The ESD protection device of claim 1 , wherein the ESD protection device is configured as any one of the following: a p-n diode, a p-i-n diode or an n-p-n device.
11. An ESD protection device, comprising:
a semiconductor body comprising an upper surface;
a plurality of p-type wells that each extend from the upper surface into the semiconductor body;
a plurality of n-type wells that each extend from the upper surface into the semiconductor body;
a plurality of electrical isolation regions in the semiconductor body around each of the p-type wells; and
separating semiconductor regions of semiconductor material from the semiconductor body between the n-type wells and the p-type wells,
wherein the separating semiconductor regions are disposed closer to the n-type wells than the p-type wells.
12. The ESD protection device of claim 11 , wherein each of the p-type wells and the n-type wells are spaced apart from one another in the first direction, wherein each of the p-type wells and the n-type wells have an elongated rectangle geometry, and wherein elongated sides of the p-type wells and the n-type wells run parallel to a second direction that is perpendicular to the first direction.
13. The ESD protection device of claim 12 , wherein a distance between a first one of the elongated sidewalls from the n-type wells to the nearest interruption is less than a distance between a first one of the elongated sidewalls from the p-type wells to the nearest interruption.
14. The ESD protection device of claim 12 , wherein a distance between a first shortened sidewall from the n-type wells to the nearest interruption is less than a distance between a first shortened sidewall from the p-type wells to the nearest interruption.
15. The ESD protection device of claim 12 , wherein the separating semiconductor regions completely separate the electrical isolation regions surrounding the p-type wells from one another.
16. The ESD protection device of claim 12 , wherein the first isolation regions are provided by a continuous dielectric region in the semiconductor body that surrounds multiple ones of the p-type wells, and wherein the separating semiconductor regions comprise enclosed rings of semiconductor material from the semiconductor body that surround the n-type wells.
17. The ESD protection device of claim 11 , wherein the ESD protection device is configured as a silicon controlled rectifier.
18. The ESD protection device of claim 11 , wherein the ESD protection device is configured as any one of the following: a p-n diode, a p-i-n diode or an n-p-n device.