Display device
A display device includes a plurality of pixels each including: a first driving transistor including a first electrode connected to a first node; a second electrode connected to a second node, and a gate electrode connected to a third node, a second driving transistor including a first electrode connected to a fourth node, a second electrode connected to the first node, a gate electrode connected to the third node, and a lower gate electrode which receives an emission control signal; a second transistor including a first electrode which receives a data voltage, a second electrode connected to the first node, and a gate electrode which receives a write gate signal; and a third transistor including a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode which receives the write gate signal or a compensation gate signal.
1 . A display device, comprising:
a plurality of pixels each including:
a first driving transistor including a first electrode connected to a first node, a second electrode connected to a second node, and a gate electrode connected to a third node;
a second driving transistor including a first electrode connected to a fourth node, a second electrode connected to the first node, a gate electrode connected to the third node, and a lower gate electrode which receives an emission control signal;
a second transistor including a first electrode which receives a data voltage, a second electrode connected to the first node, and a gate electrode which receives a write gate signal;
a third transistor including a first electrode connected to the second node, a second electrode connected to the third node, and a gate electrode which receives the write gate signal or a compensation gate signal; and
a fifth transistor including a first electrode which receives a driving voltage, a second electrode connected to the fourth node, a gate electrode which receives the emission control signal, and a lower gate electrode physically and directly connected to the lower gate electrode of the second driving transistor,
wherein the lower gate electrode of the fifth transistor receives the emission control signal through the lower gate electrode of the second driving transistor.
2 . The display device of claim 1 , wherein, in a compensation period, the data voltage is applied to the gate electrode of the first driving transistor along the second transistor, the first driving transistor, and the third transistor in response to the write gate signal or both the write gate signal and the compensation gate signal.
3 . The display device of claim 2 , wherein, in the compensation period, a threshold voltage of the first driving transistor is compensated.
4 . The display device of claim 1 , wherein each of the pixels further includes:
a fourth transistor including a first electrode which receives a first initialization voltage, a second electrode connected to the third node, and a gate electrode which receives an initialization gate signal.
5 . The display device of claim 4 , wherein, in an initialization period, the first initialization voltage initializes the gate electrode of the first driving transistor and the gate electrode of the second driving transistor in response to the initialization gate signal.
6 . The display device of claim 4 , wherein each of the third transistor and the fourth transistor is an NMOS transistor.
7 . The display device of claim 4 , wherein each of the third transistor and the fourth transistor is a PMOS transistor.
8 . The display device of claim 1 , wherein each of the pixels further includes:
a sixth transistor including a first electrode connected to the second node, a second electrode connected to a fifth node, and a gate electrode which receives the emission control signal.
9 . The display device of claim 8 , wherein each of the pixels further includes:
a light emitting element including a first electrode connected to the fifth node and a second electrode which receives a common voltage.
10 . The display device of claim 9 , wherein, in an emission period, the driving voltage is applied to the first electrode of the light emitting element along the fifth transistor, the second driving transistor, the first driving transistor, and the sixth transistor in response to the emission control signal.
11 . The display device of claim 10 , wherein, in the emission period, a threshold voltage of the second driving transistor is about 0 voltage (V).
12 . The display device of claim 9 , wherein each of the pixels further includes:
a seventh transistor including a first electrode connected to the fifth node, a second electrode which receives a second initialization voltage, and a gate electrode which receives a bypass gate signal.
13 . The display device of claim 12 , wherein each of the first driving transistor, the second driving transistor, the second transistor, the fifth transistor, the sixth transistor, and the seventh transistor is a PMOS transistor.
14 . The display device of claim 1 , wherein each of the pixels further includes:
a storage capacitor including a first electrode connected to the third node and a second electrode which receives a driving voltage.