Delay line structure and delay jitter correction method thereof

1. A delay jitter correction method of a delay line for correcting delay jitter of a delay line structure, the delay line structure comprising: N delay units and N selectors, wherein an output end of the N−1th delay unit is connected to a first input end of the N−1th selector and an input end of the Nth delay unit, the N−1th selector inputs a N−1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N−1th selector, and the Nth selector inputs a Nth selection signal, each of the delay units and each of the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first delay units are connected with input signals and the output ends of the first selectors are connected with output signals; the delay jitter correction method comprising the steps of:

Step 1, obtaining a set of clock signals having a fixed phase relationship through a Phase-locked-Loop (PLL) circuit, wherein the set of clock signals comprise a 0-degree clock signal clk_ 0 and a 90-degree clock signal clk_ 90 ;

Step 2, inputting the 0-degree clock signal clk_ 0 into the delay line to obtain a 0-degree clock delay signal clk_ 0 _delay;

Step 3, inputting the 0-degree clock delay signal clk_ 0 _delay into a D trigger and collecting the 0-degree clock delay signal clk_ 0 _delay using the 90-degree clock signal clk_ 90 ; and

Step 4, inputting an output signal of the D trigger into a judgment module to obtain a delay setting of the delay line.

2. The delay jitter correction method of a delay line of claim 1 , wherein in Step 4, the number of the delay setting of the delay line is increased one by one when an output of the D trigger is at a high level, and a delay setting when the output of the D trigger is at a low level is the delay setting of the delay line.

3. The delay jitter correction method of a delay line of claim 1 , wherein each of the selectors comprises a first NAND gate, a second NAND gate, a third NAND gate and a second inverter, a second input end of the first NAND gate is connected to a second input end of the second NAND gate via the second inverter, an output end of the first NAND gate is connected to a first input end of the third NAND gate, and an output end of the second NAND gate is connected to a second input end of the third NAND gate.

4. The delay jitter correction method of a delay line of claim 3 , wherein the first NAND gate, the second NAND gate, and the third NAND gate have the same structure, the first NAND gate comprises a first NPN transistor, a second NPN transistor, a first PNP transistor and a second PNP transistor; and

wherein a collector of the first NPN transistor is connected to VCC, a base of the first NPN transistor is connected to a base of the first PNP transistor and serves as the first input end of the first NAND gate, an emitter of the first NPN transistor is connected to an emitter of the second NPN transistor and a collector of the first PNP transistor, respectively, and serves as an output end of the first NAND gate, a collector of the second NPN transistor is connected to VCC, a base of the second NPN transistor is connected to a base of the second PNP transistor and serves as the second input end of the first NAND gate, an emitter of the first PNP transistor is connected to a collector of the second PNP transistor, and an emitter of the second PNP transistor is grounded.

5. The delay jitter correction method of a delay line of claim 3 , wherein the second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series between VCC and ground.

6. A delay jitter correction method of a delay line for correcting delay jitter of a delay line structure, the delay line structure comprising: N delay units and N selectors, wherein an output end of the N−1th delay unit is connected to a first input end of the N−1th selector and an input end of the Nth delay unit, the N−1th selector inputs a N−1th selection signal, an output end of the Nth delay unit is connected to a first input end of the Nth selector, an output end of the Nth selector is connected to a second input end of the N−1th selector, and the Nth selector inputs a Nth selection signal, each of the delay units and each of the selectors are stacked forwards according to the above-mentioned rule until the input ends of the first delay units are connected with input signals and the output ends of the first selectors are connected with output signals, each of the delay units comprises two cascaded first inverters; the delay jitter correction method comprising the steps of:

Step 1, obtaining a set of clock signals having a fixed phase relationship through a Phase-locked-Loop (PLL) circuit, wherein the set of clock signals comprise a 0-degree clock signal clk_ 0 and a 90-degree clock signal clk_ 90 ;

Step 2, inputting the 0-degree clock signal clk_ 0 into the delay line to obtain a 0-degree clock delay signal clk_ 0 _delay;

Step 3, inputting the 0-degree clock delay signal clk_ 0 _delay into a D trigger and collecting the 0-degree clock delay signal clk_ 0 _delay using the 90-degree clock signal clk_ 90 ; and

Step 4, inputting an output signal of the D trigger into a judgment module to obtain a delay setting of the delay line.

7. The delay jitter correction method of a delay line of claim 6 , wherein in Step 4, the number of the delay setting of the delay line is increased one by one when an output of the D trigger is at a high level, and a delay setting when the output of the D trigger is at a low level is the delay setting of the delay line.

8. The delay jitter correction method of a delay line of claim 6 , wherein each of the first inverters comprises a first PMOS transistor and a first NMOS transistor connected in series between VCC and ground.

9. The delay jitter correction method of a delay line of claim 6 , wherein each of the selectors comprises a first NAND gate, a second NAND gate, a third NAND gate and a second inverter, a second input end of the first NAND gate is connected to a second input end of the second NAND gate via the second inverter, an output end of the first NAND gate is connected to a first input end of the third NAND gate, and an output end of the second NAND gate is connected to a second input end of the third NAND gate.

10. The delay jitter correction method of a delay line of claim 9 , wherein the first NAND gate, the second NAND gate, and the third NAND gate have the same structure, the first NAND gate comprises a first NPN transistor, a second NPN transistor, a first PNP transistor and a second PNP transistor; and

wherein a collector of the first NPN transistor is connected to VCC, a base of the first NPN transistor is connected to a base of the first PNP transistor and serves as the first input end of the first NAND gate, an emitter of the first NPN transistor is connected to an emitter of the second NPN transistor and a collector of the first PNP transistor, respectively, and serves as an output end of the first NAND gate, a collector of the second NPN transistor is connected to VCC, a base of the second NPN transistor is connected to a base of the second PNP transistor and serves as the second input end of the first NAND gate, an emitter of the first PNP transistor is connected to a collector of the second PNP transistor, and an emitter of the second PNP transistor is grounded.

11. The delay jitter correction method of a delay line of claim 9 , wherein the second inverter comprises a second PMOS transistor and a second NMOS transistor connected in series between VCC and ground.