Non-volatile memory octo mode program and erase operation method with reduced test time

1. A non-volatile memory device, comprising:

a memory cell array comprising M word lines and N bit lines;

a control logic device, configured to receive an external signal, and output an octo signal, a program signal and an erase signal;

an address decoder, configured to receive the octo signal, and output a word line selection signal and a bit line selection signal;

a high voltage generator, configured to receive the program signal and the erase signal, and output a read voltage and a write voltage;

a row decoder, configured to receive the word line selection signal, and select a word line of the memory cell array;

a column decoder, configured to receive the bit line selection signal, and select a bit line of the memory cell array;

a page buffer, configured to receive the read voltage and the write voltage, and save data to be programmed; and

a data latch, configured to save read data obtained from a read operation;

wherein the non-volatile memory device is configured to simultaneously select non-contiguous word lines that are located every eighth word line among the M word lines and correspond to octo rows in response to the octo signal being applied to the address decoder,

wherein a write voltage is configured to be applied to memory cells connected to the word lines corresponding to the octo rows, and

wherein a voltage that is different from the write voltage is configured to be applied to memory cells connected to word lines, except for the word lines corresponding to the octo-rows.

2. The non-volatile memory device of claim 1 , wherein the data latch is further configured to receive write data, and output read data.

3. The non-volatile memory device of claim 1 , wherein the non-volatile memory device is configured to perform a write operation of a FN tunneling method.

4. The non-volatile memory device of claim 1 , wherein the memory cell array comprises a 64 KB EEPROM which has 512 word lines.

5. The non-volatile memory device of claim 1 , wherein the control logic device is further configured to generate a signal to select set of 16 word lines among a plurality of word lines of the memory cell array.

6. The non-volatile memory device of claim 1 , wherein the control logic device is further configured to generate a signal to select a set of 32 word lines among a plurality of word lines of the memory cell array.

7. A non-volatile memory device test time reduction method, the method comprising:

transmitting an octo signal from a control logic device to an address decoder;

transmitting the octo signal from the address decoder to a row decoder;

transmitting the octo signal from the row decoder to a memory cell array;

simultaneously selecting non-contiguous word lines that are located every eighth word line among the M word lines of the memory cell array and correspond to octo rows in response to the octo signal being applied to the address decoder; and

performing a write operation simultaneously in memory cells connected to the word lines corresponding to the octo rows.

8. The method of claim 7 , further comprising delivering a write signal from the control logic device to a high voltage generator.

9. The method of claim 8 , further comprising supplying a write voltage from the high voltage generator to the memory cell array.

10. The method of claim 9 , wherein the write operation is performed by supplying the write voltage to a memory cell connected to the word lines corresponding to the octo rows.

11. The method of claim 10 , further comprising applying a voltage that is different from the write voltage to a memory cell that is not connected to the word lines corresponding to the octo rows.

12. The method of claim 8 , wherein the write operation comprises an octo array erase mode, and

wherein the octo array erase mode is controlled by a write enable signal (WEB) and an erase enable signal (ERSB) supplied from the control logic device.

13. The method of claim 8 , wherein the write operation comprises an octo array program mode, and

wherein the octo array program mode is controlled by a write enable signal (WEB) and a program enable signal (PGMB) supplied from the control logic device.

14. A non-volatile memory device, comprising:

a memory cell array comprising M word lines and N bit lines;

a control logic device, configured to output an octo signal, a program signal, and an erase signal;

an address decoder, configured to receive the octo signal, and output a word line selection signal and a bit line selection signal; and

a high voltage generator, configured to receive the program signal and the erase signal, and output a read voltage and a write voltage;

wherein the non-volatile memory device is configured to select non-contiguous word lines that are located every eighth word line among the M word lines of the memory cell array and correspond to octo rows in response to the octo signal being applied to the address decoder.

15. The non-volatile memory device of claim 14 , wherein the non-volatile memory device is further configured to apply the write voltage to memory cells connected to the word lines corresponding to the octo rows, and configured to apply a voltage different from the write voltage to memory cells connected to word lines other than the word lines corresponding to the octo rows.