Low drop-out regulators and power management integrated circuits including the same

1. A low drop-out (LDO) regulator, comprising:

a voltage-to-time converter (VTC) responsive to a reference voltage and an output voltage, which is fed-back from an output node, said VTC configured to generate a voltage pulse signal having: (i) a sign associated with a magnitude of the output voltage relative to a magnitude of the reference voltage, and (ii) a first pulse width proportional to a difference in magnitude between the output voltage and the reference voltage;

a driving time-to-current converter (TIC) configured to drive a gate node with a non-zero driving current having a magnitude proportional to the first pulse width of the voltage pulse signal, in response to the sign of the voltage pulse signal indicating that the relative magnitude of the output voltage to the reference voltage has a non-zero value;

a slew adjusting circuit configured to drive the gate node with a non-zero slew adjusting current, in response to the first pulse width of the voltage pulse signal being equal to or greater than a reference time interval;

a pass transistor having a gate terminal electrically connected to the gate node, a first current carrying terminal responsive to an input voltage, and a second current carrying terminal electrically coupled to the output node; and

a compensation TIC configured to drive the output node with a non-zero compensation current having a magnitude proportional to the first pulse width of the voltage pulse signal, in response to the sign of the voltage pulse signal indicating that the relative magnitude of the output voltage to the reference voltage has a non-zero value.

2. The LDO regulator of claim 1 , wherein the VTC is configured to generate the voltage pulse signal having an on-time corresponding to the first pulse width as a down signal in response to the sign indicating that the output voltage is less than the reference voltage; and wherein the driving TIC is configured to discharge the gate node in response to the down signal.

3. The LDO regulator of claim 1 , wherein the VTC is configured to generate the voltage pulse signal having an on-time corresponding to the first pulse width as an up signal in response to the sign indicating that the output voltage is greater than the reference voltage; and wherein the driving TIC is configured to drive the gate node in response to the up signal.

4. The LDO regulator of claim 1 , wherein the VTC includes:

a first voltage controlled delay line, which is configured to output a first delayed clock signal by delaying a clock signal based on a magnitude of the reference voltage;

a second voltage controlled delay line, which is configured to output a second delayed clock signal by delaying the clock signal based on a magnitude of the output voltage; and

a phase/frequency detector configured to: (i) detect a phase difference between the first delayed clock signal and the second delayed clock signal, and (ii) generate the voltage pulse signal including a down signal or an up signal having an on-time corresponding to the first pulse width based on the phase difference between the first delayed clock signal and the second delayed clock signal.

5. The LDO regulator of claim 4 , wherein the first voltage controlled delay line includes:

a plurality of first inverters, which are: (i) cascaded in series, (ii) configured to receive the clock signal, and (iii) configured to output the first delayed clock signal by delaying the clock signal; and

a plurality of first n-channel metal-oxide semiconductor (NMOS) transistors, which are each connected between a corresponding one of odd inverters from among the plurality of first inverters and a ground voltage, and have respective gates responsive to the reference voltage, and

wherein the second voltage controlled delay line includes:

a plurality of second inverters which are: (i) cascaded in series, (ii) configured to receive the clock signal, and (iii) configured to output the second delayed clock signal by delaying the clock signal; and

a plurality of second NMOS transistors, which are connected between a corresponding one of odd inverters from among the plurality of second inverters and the ground voltage, and have respective gates responsive to the output voltage.

6. The LDO regulator of claim 1 , wherein the VTC includes:

a first voltage controlled delay line configured to output a first delayed clock signal by delaying a clock signal based on a magnitude of the reference voltage;

a second voltage controlled delay line configured to output a second delayed clock signal by delaying the clock signal based on a magnitude of the output voltage;

a time amplifier configured to amplify the first delayed clock signal and the second delayed clock signal; and

a phase/frequency detector configured to: (i) detect a phase difference between the amplified first delayed clock signal and the amplified second delayed clock signal, and (ii) generate the voltage pulse signal, including a down signal or an up signal having an on-time corresponding to the pulse width, based on the detected phase difference.

7. The LDO regulator of claim 1 , wherein the slew adjusting circuit includes:

slew detection logic configured to: (i) receive the voltage pulse signal, (ii) detect that the first pulse width of the voltage pulse signal is equal to or greater than a reference time interval during a switching period of the LDO regulator, and (iii) generate a slew detection signal having a second pulse width corresponding a difference between the first pulse width and the reference time interval; and

a slew adjusting TIC configured to receive the slew detection signal and drive the gate node with the slew adjusting current proportional to the second pulse width of the slew detection signal.

8. The LDO regulator of claim 7 , wherein the slew detection logic includes:

a delay circuit configured to delay the voltage pulse signal by a first delay amount; and

an AND gate configured to perform an AND operation on the voltage pulse signal and an output of the delay circuit, and generated the slew detection signal; and

wherein the first delay amount of the delay circuit corresponds to the reference time interval.

9. The LDO regulator of claim 7 , wherein the slew adjusting TIC includes:

an n-channel metal-oxide semiconductor (NMOS) transistor connected between the gate node and the ground voltage; and

a p-channel metal-oxide semiconductor (PMOS) transistor connected between the input voltage and the gate node;

wherein the NMOS transistor is turned-on to connect the gate node to the ground voltage in response to a down signal, if the output voltage is smaller than the reference voltage and the first pulse width is equal to or greater than the reference time interval, and

wherein the PMOS transistor is turned-on to drive the gate node with the slew adjusting current in response to an up signal, if the output voltage is greater than the reference voltage and the first pulse width is equal to or greater than the reference time interval.

10. A low drop-out (LDO) regulator, comprising:

a voltage to time converter (VTC) configured to receive a reference voltage and an output voltage provided from an output node, and configured to generate a voltage pulse signal having a sign and a first pulse width, the sign being associated with a relative magnitude of the output voltage with respect to the reference voltage, the first pulse width being proportional to a difference between the reference voltage and the output voltage;

a driving time to current converter (TIC) configured to charge or discharge a gate node with a driving current proportional to the first pulse width of the voltage pulse signal in response to the sign indicating that the relative magnitude has a non-zero value, based on the voltage pulse signal;

a slew adjusting circuit configured to be activated in response to the first pulse width of the voltage pulse signal being equal to or greater than a reference time interval and configured to charge or discharge the gate node with a slew adjusting current based on the voltage pulse signal;

a pass transistor connected to the gate node, the pass transistor configured to regulate an input voltage to provide the output voltage to an output node, based on the driving current and selectively based on the slew adjusting current; and

a compensation TIC configured to charge or discharge the output node with a compensation current corresponding to the first pulse width of the voltage pulse, in response to the sign indicating that the relative magnitude has a non-zero value, based on the voltage pulse signal.

11. The LDO regulator of claim 10 , wherein:

the VTC is configured to generate the voltage pulse signal having an on-time corresponding to the first pulse width as a down signal in response to the sign indicating that the output voltage is smaller than the reference voltage; and

the driving TIC is configured to discharge the gate node in response to the down signal.

12. The LDO regulator of claim 10 , wherein:

the VTC is configured to generate the voltage pulse signal having an on-time corresponding to the first pulse with as an up signal in response to the sign indicating that the output voltage is greater than the reference voltage; and

the driving TIC is configured to provide the driving current to the gate node in response to the up signal.

13. The LDO regulator of claim 10 , wherein the VTC includes:

a first voltage controlled delay line configured to output a first delayed clock signal by delaying a clock signal based on the reference voltage;

a second voltage controlled delay line configured to output a second delayed clock signal by delaying the clock signal based on the output voltage; and

a phase/frequency detector configured to detect a phase difference between the first delayed clock signal and the second delayed clock signal and configured to generate the voltage pulse signal including a down signal or an up signal having an on-time corresponding to the first pulse width based on the phase difference.

14. The LDO regulator of claim 13 , wherein the first voltage controlled delay line includes:

a plurality of first inverters which are cascaded connected, the plurality of first inverters configured to receive the clock signal and configured to output the first delayed clock signal by delaying the clock signal; and

a plurality of first n-channel metal-oxide semiconductor (NMOS) transistors, each of the first NMOS transistor connected between corresponding one of odd inverters from among the plurality of first inverters and a ground voltage, each of the first NMOS transistors having a gate to receive the reference voltage, and

wherein the second voltage controlled delay line includes:

a plurality of second inverters which are cascaded connected, the plurality of second inverters configured to receive the clock signal and configured to output the second delayed clock signal by delaying the clock signal; and

a plurality of second NMOS transistors, each of the second NMOS transistor connected between corresponding one of odd inverters from among the plurality of second inverters and the ground voltage, each of the second NMOS transistors having a gate to receive the output voltage.

15. The LDO regulator of claim 10 , wherein the VTC includes:

a first voltage controlled delay line configured to output a first delayed clock signal by delaying a clock signal based on the reference voltage;

a second voltage controlled delay line configured to output a second delayed clock signal by delaying the clock signal based on the output voltage;

a time amplifier configured to amplify the first delayed clock signal and the second delayed clock signal; and

a phase/frequency detector configured to detect a phase difference between the amplified first delayed clock signal and the amplified second delayed clock signal and configured to generate the voltage pulse signal including a down signal or an up signal having an on-time corresponding to the pulse with based on the phase difference.

16. The LDO regulator of claim 10 , wherein the slew adjusting circuit includes:

a slew detection logic configured to receive the voltage pulse signal, configured to detect that the first pulse width of the voltage pulse signal is equal to or greater than a reference time interval during a switching period of the LDO regulator and configured to generate a slew detection signal having a second pulse width corresponding a difference between the first pulse width and the reference time interval; and

a slew adjusting TIC configured to receive the slew detection signal and configured to provide the gate node with the slew adjusting current proportional to the second pulse width of the slew detection signal.

17. The LDO regulator of claim 16 , wherein the slew detection logic includes:

a delay circuit configured to delay the voltage pulse signal by a first delay amount; and

an AND gate configured to perform an AND operation on the voltage pulse signal and an output of the delay circuit to output the slew detection signal,

wherein the first delay amount of the delay circuit corresponds to the reference time interval.

18. The LDO regulator of claim 16 , wherein slew adjusting TIC includes:

an n-channel metal-oxide semiconductor (NMOS) transistor connected between the gate node and the ground voltage; and

a p-channel metal-oxide semiconductor (PMOS) transistor connected between the input voltage and the gate node,

wherein the NMOS transistor is turned-on to connect the gate node to the ground voltage in response to a down signal corresponding to the slew detection signal having an on-time corresponding to a second pulse width corresponding to a difference between the first pulse width and the reference time interval, if the output voltage is smaller than the reference voltage and the first pulse width is equal to or greater than the reference time interval, and

wherein the PMOS transistor is turned-on to provide the gate node with the slew adjusting current based on the input voltage in response to an up signal corresponding to the slew detection signal having an on-time corresponding to the second pulse width corresponding to a difference between the first pulse width and the reference time interval, if the output voltage is greater than the reference voltage and the first pulse width is equal to or greater than the reference time interval.

19. The LDO regulator of claim 10 , wherein the compensation TIC includes:

a p-channel metal-oxide semiconductor (PMOS) transistor connected between the input voltage and the output node; and

an n-channel metal-oxide semiconductor (NMOS) transistor connected between the output node and the ground voltage,

wherein the PMOS transistor is turned-on to provide the output node with the compensation current based on the input voltage in response to an up signal corresponding to the voltage pulse signal having an on-time corresponding to the first pulse width, if the output voltage is smaller than the reference voltage, and

wherein the NMOS transistor is turned-on to connect the output node to the ground voltage in response to inverted up signal having an on-time corresponding to the first pulse width, if the output voltage is greater than the reference voltage.

20. A low drop-out (LDO) regulator, comprising:

a voltage to time converter (VTC) configured to receive a reference voltage and an output voltage provided from an output node, and configured to generate a voltage pulse signal having a sign and a first pulse width, the sign being associated with a relative magnitude of the output voltage with respect to the reference voltage, the pulse with being proportional to a difference between the reference voltage and the output voltage;

a driving time to current converter (TIC) configured to charge or discharge a gate node with a driving current proportional to the pulse with of the voltage pulse signal in response to the sign indicating that the relative magnitude has a non-zero value, based on the voltage pulse signal;

a slew adjusting circuit configured to be activated in response to the pulse with of the voltage pulse signal being equal to or greater than a reference time interval and configured to charge or discharge the gate node with a slew adjusting current based on the voltage pulse signal to increase a slew rate of the output voltage;

a pass transistor connected to the gate node, the pass transistor configured to regulate an input voltage to provide the output voltage to an output node, based on the driving current and selectively based on the slew adjusting current; and

a compensation TIC configured to charge or discharge the output node with a compensation current corresponding to the first pulse width of the voltage pulse, in response to the sign indicating that the relative magnitude has a non-zero value, based on the voltage pulse signal, and

wherein the slew adjusting circuit is:

configured to detect that the pulse with of the voltage pulse signal is equal to or greater than a reference time interval during a switching period of the LDO regulator and configured to generate a slew detection signal having a second pulse width corresponding a difference between the first pulse width and the reference time interval; and

configured to provide the gate node with the slew adjusting current proportional to the second pulse width of the slew detection signal.