Set of integrated standard cells

1. An integrated circuit, comprising:

a silicon-on-insulator substrate;

at least a first standard cell framed by two second standard cells, the three cells being disposed adjacent to each other, each cell including:

at least two NMOS transistors and at least two PMOS transistors located in and on the silicon-on-insulator substrate, the at least two PMOS transistors of the first standard cell having a channel including silicon and germanium, the at least two NMOS transistors of each second standard cell having a silicon channel and a threshold voltage different in absolute value from a threshold voltage of the at least two PMOS transistors of the first standard cell.

2. The integrated circuit according to claim 1 , comprising a semiconductor connection region coupling an active area of at least one of the at least two PMOS transistors of the first standard cell and an active area of the PMOS transistors of the second standard cells.

3. The integrated circuit according to claim 2 , comprising at least two standard filling cells adjacent to the first standard cell, respectively disposed between the first standard cell and the two second standard cells, respectively butted to the first standard cell and to the two second standard cells, each of the at least two standard filling cells including a filling region having a first part containing silicon and germanium in contact with the active area at least one of the at least two PMOS transistors of the first standard cell and a second part containing silicon in contact with the active area of at least one of the at least two PMOS transistors of the second corresponding standard cell, and two first polysilicon lines located above a border between the filling cell and the first standard cell or the second standard cell respectively, and configured to be biased at a supply voltage, the filling regions forming the semiconductor connection region.

4. The integrated circuit according to claim 1 , comprising at least two standard cells called filling cells framing the first standard cell, respectively disposed between the first standard cell and the two second standard cells, respectively butted to the first standard cell and to the two second standard cells, each filling cell including a filling region containing silicon and germanium, adjoined to the active area of at least one of the at least two PMOS transistors of the first standard cell and at least a first polysilicon line located above the filling region and configured to remain electrically floating, the filling regions being separated from the active area of at least one of the at least two PMOS transistors of each second standard cell by an insulating region.

5. The integrated circuit according to claim 2 , wherein at least one of the at least two PMOS transistors of the first standard cell is a low voltage threshold transistor and at least one of the at least two PMOS transistors of the second standard cell is a high voltage threshold transistor.

6. The integrated circuit according to claim 2 , wherein at least one of the at least two PMOS transistors of the first standard cell is a regular voltage threshold transistor and at least one of the at least two PMOS transistors of the second standard cell is a high voltage threshold transistor.

7. The integrated circuit according to claim 1 , wherein at least one of the at least two NMOS transistors of the first standard cell has a silicon channel and a threshold voltage equal to or greater in absolute value than the threshold voltage of at least one of the at least two PMOS transistors of the first standard cell, and the active area of at least one of the at least two PMOS transistors of the first standard cell is electrically insulated from the active area of at least one of the at least two PMOS transistors of each second standard cell.

8. The integrated circuit according to claim 7 , wherein the first standard cell is adjoined to each second standard cell.

9. The integrated circuit according to claim 7 , wherein at least one of the at least two NMOS transistors of the first cell is a regular voltage threshold transistor, at least one of the at least two PMOS transistors of the first cell is a low voltage threshold transistor and at least one of the at least two PMOS transistors of each second cell is a high voltage threshold transistor.

10. The integrated circuit according to claim 7 , further comprising another set of a first additional standard cell framed by two second additional standard cells, the three additional cells being adjoined and each including at least one NMOS transistor having a silicon channel and at least one PMOS transistor having a channel containing silicon and germanium, the active areas of all PMOS transistors forming a continuous semiconductor area, the threshold voltage of the at least one PMOS transistor of the first additional standard cell being different in absolute value from the threshold voltage of the at least one PMOS transistors of the second additional standard cells and the integrated circuit further including two polysilicon lines configured to be biased at a supply voltage and respectively disposed above the border between the active area of the at least one PMOS transistor of the first additional standard cell and the at least one PMOS transistor of each second additional standard cell.

11. The integrated circuit according to claim 10 , wherein the at least one PMOS transistor of the first additional standard cell is a low voltage threshold transistor and the PMOS transistors of the second additional standard cells are regular voltage threshold transistors.

12. The integrated circuit according to claim 1 , wherein the silicon-on-insulator type substrate is a fully depleted silicon-on-insulator type substrate.