Multilayer capacitor and method of manufacturing the same

1. A multilayer capacitor, comprising:

a capacitor body including first and second surfaces opposing each other in a first direction of the capacitor body, third and fourth surfaces opposing each other in a second direction of the capacitor body, and fifth and sixth surface disposed in a third direction of the capacitor body, and including a plurality of dielectric layers, and first and second internal electrodes alternately disposed in the first direction with the dielectric layer interposed therebetween; and

first and second external electrodes disposed on both ends of the capacitor body in the second direction, respectively,

wherein the first internal electrode includes a first capacitance forming portion, a first lead-out portion extending from the first capacitance forming portion toward the third surface of the capacitor body and connected to the first external electrode, and a first dot pattern portion disposed in at least one corner of the first capacitance forming portion, and

wherein the second internal electrode includes a second capacitance forming portion overlapping the first capacitance forming portion in the first direction, a second lead-out portion extending from the second capacitance forming portion toward the fourth surface of the capacitor body and connected to the second external electrode, and a second dot pattern portion disposed in at least one corner of the second capacitance forming portion.

2. The multilayer capacitor of claim 1 , wherein the first dot pattern portion and the second dot pattern portion have dot patterns not overlapping each other in the first direction.

3. The multilayer capacitor of claim 1 , wherein lengths of the first and second lead-out portions in the third direction are less than lengths in the third direction of the first and second capacitance forming portions, respectively.

4. The multilayer capacitor of claim 1 ,

wherein, in the first dot pattern portion, a dot-shaped first electrode portion and a first space portion are alternately disposed in the second and third directions, and

wherein, in the second dot pattern portion, a dot-shaped second electrode portion and a second space portion are alternately disposed in the second and third directions.

5. The multilayer capacitor of claim 4 ,

wherein the first electrode portion overlaps the second space portion in the first direction, and

wherein the second electrode portion overlaps the first space portion in the first direction.

6. The multilayer capacitor of claim 4 ,

wherein an average thickness of the first electrode portion is 70 to 90% of an average thickness of the first capacitance forming portion, and

wherein an average thickness of the second electrode portion is 70 to 90% of an average thickness of the second capacitance forming portion.

7. The multilayer capacitor of claim 1 , wherein the capacitor body includes an active region in which the first and second capacitance forming portions overlap each other in the first direction, and upper and lower cover regions disposed on upper and lower surfaces of the active region, respectively.

8. The multilayer capacitor of claim 1 , wherein the first and second external electrodes includes:

first and second connection portions disposed on the third and fourth surfaces of the capacitor body, respectively; and

first and second band portions extending from the first and second connection portions to a portion of the first surface of the capacitor body, respectively.

9. A method of manufacturing a multilayer capacitor, the method comprising:

forming first and second internal electrodes on first and second ceramic sheets, respectively;

forming a laminate by laminating a plurality of first and second ceramic sheets on which the first and second internal electrodes are formed such that the first and second internal electrodes oppose each other with the first and second ceramic sheets interposed therebetween and pressing the first and second ceramic sheets;

forming a capacitor body including first and second surfaces opposing each other in a first direction of the capacitor body, third and fourth surfaces opposing each other in a second direction of the capacitor body, and fifth and sixth surface disposed in a third direction of the capacitor body, and including first and second lead-out portions of the first and second internal electrodes exposed through the third and fourth surfaces, respectively, by cutting the laminate at each region corresponding to a single capacitor and performing baking; and

forming first and second external electrodes on the capacitor body to be electrically connected to the first and second lead-out portions, respectively,

wherein the first internal electrode includes a first capacitance forming portion, a first lead-out portion extending from the first capacitance forming portion toward the third surface of the capacitor body and connected to the first external electrode, and a first dot pattern portion formed in at least one corner of the first capacitance forming portion, and

wherein the second internal electrode includes a second capacitance forming portion overlapping the first capacitance forming portion in the first direction, a second lead-out portion extending from the second capacitance forming portion toward the fourth surface of the capacitor body and connected to the second external electrode, and a second dot pattern portion formed in at least one corner of the second capacitance forming portion.

10. The method of claim 9 , wherein the second dot pattern portion is formed to not overlap the first dot pattern portion in the first direction.

11. The method of claim 9 , wherein the first internal electrode is formed by disposing a printing screen including a wire mesh on the first ceramic sheet, applying a conductive paste to the wire mesh by a predetermined thickness, and printing a first internal electrode pattern such that one end in a length direction is formed as the first lead-out portion having a bottleneck shape on the wire mesh to which the conductive paste is applied and the first dot pattern is formed in the at least one corner, and developing an exposed conductive paste, and

wherein the second internal electrode is formed by disposing a printing screen including a wire mesh on the second ceramic sheet, applying a conductive paste to the wire mesh by a predetermined thickness, and printing a second internal electrode pattern such that the other end in the length direction is formed as the second lead-out portion having a bottleneck shape on the wire mesh to which the conductive paste is applied and the second dot pattern is formed in the at least one corner, and developing an exposed conductive paste.