Reconfigurable parallel processing
Processors, systems and methods are provided for thread level parallel processing. A processor may comprise a plurality of processing elements (PEs) that each may comprise a configuration buffer, a sequencer coupled to the configuration buffer of each of the plurality of PEs and configured to distribute one or more PE configurations to the plurality of PEs, and a gasket memory coupled to the plurality of PEs and being configured to store at least one PE execution result to be used by at least one of the plurality of PEs during a next PE configuration.
1. A processor, comprising:
a plurality of processing elements (PEs) arranged in a plurality of columns with each column including at least one PE, each of the plurality of PEs including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads, wherein the plurality of columns are coupled for data to flow from a preceding column to a succeeding column in a direction from a first column to a last column of the plurality of columns;
a sequencer coupled to the plurality of PEs and configured to distribute decoded instructions packaged as configurations to the plurality of PEs;
a temporary data storage configured to store data received from the last column and to provide the data stored to the first column;
a plurality of switch boxes (SBs) arranged in the plurality of columns with each SB associated with one of the plurality of PEs for the plurality of switch boxes to collectively provide data switching for the plurality of PEs; and
a memory unit and a plurality of memory ports (MPs), wherein each MP is arranged in a respective column of the plurality of columns, and coupled between the memory unit and a SB of the respective column for the plurality of PEs to access the memory unit.
2. The processor of claim 1 , further comprising a plurality of inter-column switch boxes (ICSBs) coupled to the sequencer to receive ICSB configurations from the sequencer, the plurality of ICSBs chained to form a data routing bus and configured to provide data switching between neighboring columns of the plurality of columns according to the ICSB configurations.
3. The processor of claim 1 , wherein the plurality of MPs are coupled to the sequencer to receive MP configurations from the sequencer and configured to operate in a private memory access mode or a shared memory access mode during one MP configuration.
4. The processor of claim 1 , wherein the plurality of PEs are identical and chained using the plurality of switch boxes to form one row of identical PEs.
5. The processor of claim 1 , wherein the plurality of PEs, the plurality of SBs and the plurality of MPs are reconfigurable units and configured to be reconfigured after repeatedly applying one respective configuration a specified number of times.
6. The processor of claim 5 , where each reconfigurable units include a configuration buffer and a counter, the configuration buffer is configured to receive respective configurations from the sequencer and the counter is used to count to the specified number of times.
7. The processor of claim 1 , wherein memory unit includes a plurality of memory banks and each memory bank is associated with a memory cache, each memory cache is coupled to all of the plurality of MPs.
8. The processor of claim 1 , wherein each PE of the plurality of PEs comprises a plurality of data buffers for the plurality of ALUs and is configured to operate independently.
9. A method, comprising:
executing a first instruction at a reconfigurable processing element (PE) in a plurality of columns a number of times according to a first configuration, the reconfigurable PE being configured to be part of a first physical data path during the first configuration;
delivering an execution result from the reconfigurable PE to a temporary data storage to temporality store the execution result after each execution of the first instruction; and
feeding the execution result stored in the temporary data storage to a second physical data path;
wherein the reconfigurable PE is one PE of a plurality of processing elements (PEs) arranged in a plurality of columns with each column including at least one PE, each of the plurality of PEs including a plurality of arithmetic logic units (ALUs) configured to execute a same instruction in parallel threads, wherein the plurality of columns are coupled for data to flow from a preceding column to a succeeding column in a direction from a first column to a last column of the plurality of columns, and the temporary data storage is configured to store data received from the last column and to provide the data stored to the first column;
wherein a sequencer is coupled to the plurality of PEs and configured to distribute decoded instructions packaged as configurations to the plurality of PEs;
wherein the processor further comprises a plurality of switch boxes (SBs) arranged in the plurality of columns with each SB associated with one of the plurality of PEs for the plurality of switch boxes to collectively provide data switching for the plurality of PEs.
10. The method of claim 9 , wherein the processor further comprises a memory unit and a plurality of memory ports (MPs), wherein each MP is arranged in a respective column of the plurality of columns, and coupled between the memory unit and a SB of the respective column for the plurality of PEs to access the memory unit.
11. The method of claim 10 , wherein the plurality of PEs, the plurality of SBs and the plurality of MPs are reconfigurable units and configured to be reconfigured after repeatedly applying one respective configuration a specified number of times.
12. The method of claim 11 , where each of the reconfigurable units includes a configuration buffer and a counter, the configuration buffer is configured to receive respective configurations from the sequencer and the counter is used to count to the specified number of times.
13. The method of claim 10 , wherein memory unit includes a plurality of memory banks and each memory bank is associated with a memory cache, each memory cache is coupled to all of the plurality of MPs.
14. The method of claim 9 , wherein each PE of the plurality of PEs comprises a plurality of data buffers for the plurality of ALUs and is configured to operate independently.
15. The method of claim 10 , wherein the processor further comprises a plurality of inter-column switch boxes (ICSBs) coupled to the sequencer to receive ICSB configurations from the sequencer, the plurality of ICSBs chained to form a data routing bus and configured to provide data switching between neighboring columns of the plurality of columns according to the ICSB configurations.
16. The method of claim 10 , wherein the plurality of MPs are coupled to the sequencer to receive MP configurations from the sequencer and configured to operate in a private memory access mode or a shared memory access mode during one MP configuration.