Fine-grained disaggregated server architecture
A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.
1 . A microelectronic assembly, comprising:
a first plurality of integrated circuit (IC) dies in a first layer, wherein:
the first plurality of IC dies comprises a first IC die, and
the first IC die comprises first conductive contacts at a first face of the first IC die;
a second plurality of IC dies in a second layer between the first layer and a third layer, wherein:
the second plurality of IC dies is in an array of rows and columns, wherein the second plurality of IC dies comprises a second IC die and a third IC die,
the second IC die comprises second conductive contacts at a second face of the second IC die,
the third IC die comprises third conductive contacts at a third face of the third IC die, and
the first conductive contacts are coupled with the second conductive contacts at a first bonding interface between the first face of the first IC die and the second face of the second IC die; and
a third plurality of IC dies in the third layer, wherein:
the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies,
the third plurality of IC dies comprises a fourth IC die,
the fourth IC die comprises fourth conductive contacts and fifth conductive contacts at a fourth face of the fourth IC die,
the fourth conductive contacts are coupled with corresponding conductive contacts at a second bonding interface between the fourth face of the fourth IC die and a face of the second IC die opposite the second face, and
the fifth conductive contacts are coupled with the third conductive contacts at a third bonding interface between the fourth face of the fourth IC die and the third face of the third IC die.
2 . The microelectronic assembly of claim 1 , wherein:
the first IC die comprises a first circuit,
the second IC die comprises a second circuit and the third IC die comprises a third circuit,
the first circuit has a greater number of electrical connections with the second circuit than with the third circuit, and
the first IC die is coupled to the second IC die with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.
3 . The microelectronic assembly of claim 1 , wherein:
the first IC die comprises a first circuit electrically coupled to a second circuit external to the first IC die,
the second IC die is proximate to the second circuit, and the third IC die is farther from the second circuit than the second IC die, and
the first IC die is coupled to the second IC die by an electrical pathway from the first circuit to the second circuit that is shorter than another electrical pathway to the second circuit from the third IC die.
4 . The microelectronic assembly of claim 1 , wherein:
the first plurality of IC dies comprises a first IC die having a first intellectual property (IP) core and a an additional IC die having a second IP core,
the first IP core is conductively coupled with the second IP core,
the second plurality of IC dies comprises the second IC die, and
the first IC die and the additional IC die are coupled to the second IC die with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.
5 . The microelectronic assembly of claim 1 , whereof the first plurality of IC dies comprises transistors that are smaller than transistors of the second plurality of IC dies.
6 . The microelectronic assembly of claim 1 , wherein the first IC die of the first plurality of IC dies comprises transistors that are smaller than transistors in the second IC die of the first plurality of IC dies.
7 . The microelectronic assembly of claim 6 , wherein the first IC die does not comprise transistors having ferromagnetic materials, and the second IC die comprises transistors having ferromagnetic materials.
8 . The microelectronic assembly of claim 1 , further comprising a network on chip (NOC), wherein the NOC comprises:
a plurality of router circuits conductively coupled by a plurality of conductors to IP cores of the first plurality of IC dies, wherein:
each IP core of the first plurality of IC dies is conductively coupled to at least one router circuit by one or more conductors in the plurality of conductors, and
the plurality of router circuits is in the second plurality of IC dies.
9 . An IC package, comprising:
a first IC die in a first layer;
a second IC die and a third IC die in a second layer;
a fourth IC die in a third layer; and
a package substrate coupled to the third layer,
wherein:
the second layer is between the first layer and the third layer,
the first IC die is attached to the second IC die via a first hybrid bonding interface between first conductive contacts of the first IC die and second conductive contacts of the second IC die,
the third IC die is adjacent to the second IC die,
the fourth IC die comprises a conductive pathway between the second IC die and the third IC die,
the second IC die is attached to the fourth IC die via a second hybrid bonding interface between third conductive contacts of the second IC die and fourth conductive contacts of the fourth IC die, and
the third IC die is attached to the fourth IC die via a third hybrid bonding interface between fifth conductive contacts of the third IC die and sixth conductive contacts of the fourth IC die.
10 . The IC package of claim 9 , wherein: the second IC die comprises a circuit conductively coupled to one or more IP cores of a first plurality of IC dies of the first layer.
11 . The IC package of claim 10 , wherein at least one of the IP cores comprises a processor circuitry, and the circuit comprises a voltage regulator circuit.
12 . The IC package of claim 9 , wherein the second IC die comprises a stacked plurality of IC dies, each IC die in the stacked plurality of IC dies comprising transistors having a ferromagnetic material.
13 . The IC package of claim 9 , wherein the fourth IC die lacks transistors.
14 . The IC package of claim 9 , wherein the second IC die, the third IC die and the fourth IC die comprise through-substrate vias (TSVs).
15 . The IC package of claim 9 , wherein the fourth IC die is embedded in a dielectric material.
16 . The IC package of claim 15 , wherein through-dielectric vias (TDVs) are in the dielectric material.
17 . An arrangement of IC dies, comprising:
a first plurality of IC dies comprising IC dies having IP cores, the first plurality of IC dies comprising a first IC die;
a second plurality of IC dies comprising a second IC die and a third IC die wherein the second IC die comprises at least one circuit conductively coupled to one or more of the IP cores;
a third plurality of IC dies comprising a fourth IC die, wherein the fourth IC die comprises at least one conductive pathway between the second plurality of IC dies with interconnects having a pitch of less than 10 micrometers,
wherein:
the first plurality of IC dies is in a first layer,
the second plurality of IC dies is in a second layer,
the second layer is between the first layer and a third layer, and
the third plurality of IC dies is in the third layer;
a first bonding interface between first conductive contacts of the first IC die and second conductive contacts of a second IC die;
a second bonding interface between third conductive contacts of the second IC die and fourth conductive contacts of the fourth IC die; and
a third bonding interface between fifth conductive contacts of the third IC die and sixth conductive contacts of the fourth IC die.
18 . The arrangement of claim 17 , wherein the IC dies of the second plurality comprise a shared cache accessible by the first plurality of IC dies.
19 . The arrangement of claim 17 , wherein the IC dies of the first plurality are coupled to the IC dies of the second plurality with interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects.
20 . The arrangement of claim 17 , wherein the IC dies of the second plurality are in a regular array of rows and columns.