Overvoltage protection for multi-chip module and system-in-package

1. An apparatus comprising:

a package encompassing at least a first integrated circuit die and a second integrated circuit die;

the first integrated circuit die attached to the package, the first integrated circuit die comprising functional integrated circuits and one or more electrical overstress/electrostatic discharge (EOS/ESD) protection circuits; and

the second integrated circuit die attached to the package, the second integrated circuit die electrically coupled to the first integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by at least one of the one or more EOS/ESD protection circuits of the first integrated circuit die, the second integrated circuit die being an integrated passive devices die without functional integrated circuits.

2. The apparatus of claim 1 , wherein the second integrated circuit die does not comprise its own one or more EOS/ESD protection circuits.

3. The apparatus of claim 1 , wherein each of at least some of the functional integrated circuits of the first integrated circuit die comprises an amplifier, an oscillator, a mixer, a filter, a phase-locked loop, a modulator, a demodulator, an encoder, a decoder, signal processor, an equalizer, a receiver, a transmitter, a timer, a microprocessor, a memory, or a converter.

4. The apparatus of claim 1 , wherein the second integrated circuit die is electrically coupled to the first integrated circuit die via an input of the first integrated circuit die such that coupling of the second integrated circuit die to the input does not alter a functionality of the functional integrated circuits of the first integrated circuit die.

5. The apparatus of claim 1 , wherein the second integrated circuit die is electrically coupled to the first integrated circuit die with bond wires.

6. The apparatus of claim 1 :

wherein the package further encompasses a third integrated circuit die;

wherein the third integrated circuit die is attached to the package, the third integrated circuit die comprising functional integrated circuits and one or more EOS/ESD protection circuits, the second integrated circuit electrically coupled to the third integrated circuit die such that at least one component of the second integrated circuit die is protected from EOS/ESD by at least one of the one or more EOS/ESD protection circuits of the third integrated circuit die; and

wherein power supply connections of the third integrated circuit die are electrically coupled to the first integrated circuit die.

7. The apparatus of claim 6 , wherein the power supply connections of the third integrated circuit die are electrically coupled to power supply connections of the first integrated circuit die with bond wires.

8. The apparatus of claim 6 , wherein the power supply connections of the third integrated circuit die are electrically coupled to power supply connections of the first integrated circuit die with one or more diodes or one or more silicon-controlled rectifiers.

9. The apparatus of claim 8 , wherein the power supply connections of the first integrated circuit die are configured to operate at first voltages, and the power supply connections of the third integrated circuit die are configured to operate at second voltages different than the first voltages.

10. The apparatus of claim 9 , wherein the power supply connections of the third integrated circuit die are electrically coupled to the power supply connections of the first integrated circuit die with one or more diodes, the one or more diodes being configured to operate in reverse-bias mode.

11. A method of providing protection from electrical overstress/electrostatic discharge (EOS/ESD), the method comprising:

assembling at least a first integrated circuit die and a second integrated circuit die within a common package, the first integrated circuit die comprising functional integrated circuits and one or more EOS/ESD protection circuits, the second integrated circuit die being an integrated passive devices die without functional integrated circuits; and

protecting at least one component of the second integrated circuit die from EOS/ESD with at least one of the one or more EOS/ESD protection circuits of the first integrated circuit die.

12. The method of claim 11 , wherein the second integrated circuit die does not comprise its own one or more EOS/ESD protection circuits.

13. The method of claim 11 , wherein each of at least some of the functional integrated circuits of the first integrated circuit die comprises an amplifier, an oscillator, a mixer, a filter, a phase-locked loop, a modulator, a demodulator, an encoder, a decoder, signal processor, an equalizer, a receiver, a transmitter, a timer, a microprocessor, a memory, or a converter.

14. The method of claim 11 , wherein the second integrated circuit die is electrically coupled to the first integrated circuit die via an input of the first integrated circuit die such that coupling of further comprises an integrated circuit die to the input does not alter a functionality of the functional integrated circuits of the first integrated circuit die.

15. The method of claim 11 , wherein the second integrated circuit die is electrically coupled to the first integrated circuit die with bond wires.

16. The method of claim 11 :

wherein said assembling further comprises assembling a third integrated circuit die within the common package, the third integrated circuit die comprising functional integrated circuits and one or more EOS/ESD protection circuits;

wherein said protecting comprises protecting at least one component of the second integrated circuit die from EOS/ESD with at least one of the one or more EOS/ESD protection circuits of the third integrated circuit die; and

wherein power supply connections of the third integrated circuit die are electrically coupled to the first integrated circuit die.

17. The method of claim 16 , wherein the power supply connections of the third integrated circuit die are electrically coupled to power supply connections of the first integrated circuit die with bond wires.

18. The method of claim 16 , wherein the power supply connections of the third integrated circuit die are electrically coupled to power supply connections of the first integrated circuit die with one or more diodes or one or more silicon-controlled rectifiers.

19. The method of claim 18 , wherein the power supply connections of the first integrated circuit die are configured to operate at first voltages, and the power supply connections of the third integrated circuit die are configured to operate at second voltages different than the first voltages.

20. The method of claim 19 , wherein the power supply connections of the third integrated circuit die are electrically coupled to the power supply connections of the integrated circuit die with one or more diodes, the one or more diodes being configured to operate in reverse-bias mode.