Display apparatus
A display apparatus includes an active area, an inactive area surrounding the active area, a pixel disposed in the active area, and a driver IC, a gate driver, a low-potential power supply line, a high-potential power supply line and a subframe controller disposed in the inactive area, wherein the subframe controller is disposed between the pixel and the gate driver.
1. A display apparatus, comprising:
an active area;
an inactive area surrounding the active area;
a pixel disposed in the active area; and
a driver IC, a gate driver, a low-potential power line, a high-potential power line and a subframe controller disposed in the inactive area,
wherein the subframe controller is disposed between the pixel and the gate driver,
wherein the driver IC includes a gate low voltage pad connected to the gate driver, and
wherein the gate low voltage pad is connected to a source electrode of the subframe controller.
2. The display apparatus according to claim 1 , wherein the driver IC includes a subframe control pad connected to a gate electrode of the subframe controller.
3. The display apparatus according to claim 2 , wherein the driver IC further includes a clock signal pad, a start signal pad and a gate high voltage pad connected to the gate driver.
4. The display apparatus according to claim 1 , wherein the driver IC further includes a gate high voltage pad connected to the gate driver.
5. The display apparatus according to claim 1 , wherein the gate low voltage is −9 V.
6. The display apparatus according to claim 1 , wherein the gate driver includes an oxide transistor.
7. The display apparatus according to claim 1 , wherein a drain electrode of the subframe controller is electrically connected to an output terminal of the gate driver, and the output terminal of the gate driver is connected to the pixel.
8. The display apparatus according to claim 1 , wherein the gate driver is driven in a 1 Hz low-speed driving mode.
9. The display apparatus according to claim 8 , wherein the subframe controller is in a turn-off state during a main frame period of the pixel and is in a turn-on state during a subframe period of the pixel.
10. The display apparatus according to claim 9 , wherein a drain electrode of the subframe controller outputs an output voltage of −9 V when the subframe controller is in a turn-on state.
11. The display apparatus according to claim 9 , wherein the main frame period is 8.3 ms.
12. The display apparatus according to claim 1 , wherein a drain electrode of the subframe controller is connected to a line extended from the gate driver to the pixel.
13. A display apparatus, comprising:
an active area;
an inactive area surrounding the active area;
a pixel disposed in the active area; and
a driver IC, a gate driver, a low-potential power line, a high-potential power line and a subframe controller disposed in the inactive area,
wherein the gate driver is driven in a low-speed driving mode,
wherein the driver IC includes a gate low voltage pad connected to the gate driver, and
wherein the gate low voltage pad is connected to a source electrode of the subframe controller.
14. The display apparatus according to claim 13 , wherein the gate driver includes an oxide transistor.
15. The display apparatus according to claim 13 , wherein the subframe controller is disposed between the pixel and the gate driver.
16. The display apparatus according to claim 15 , wherein the driver IC further includes a subframe control pad connected to a gate electrode of the subframe controller.
17. The display apparatus according to claim 16 , wherein the driver IC further includes a gate high voltage pad connected to the gate driver.
18. The display apparatus according to claim 16 , wherein the driver IC further includes a clock signal pad, a start signal pad and a gate high voltage pad connected to the gate driver.
19. The display apparatus according to claim 13 , wherein the gate low voltage is −9 V.
20. The display apparatus according to claim 13 , wherein the subframe controller is in a turn-off state during a main frame period of the pixel and is in a turn-on state during a subframe period of the pixel.
21. The display apparatus according to claim 20 , wherein a drain electrode of the subframe controller outputs an output voltage of −9 V when the subframe controller is in a turn-on state.
22. The display apparatus according to claim 20 , wherein the main frame period is 8.3 ms.
23. The display apparatus according to claim 13 , wherein a drain electrode of the subframe controller is connected to a line extended from the gate driver to the pixel.