Techniques for performing write training on a dynamic random-access memory
Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.
1. A computer-implemented method for performing a write training operation on a memory device, the method comprising:
initializing a read/write memory on the memory device with a first data pattern based on a seed value stored in a first register;
receiving a second data pattern on an input pin of the memory device;
comparing the first data pattern with the second data pattern to generate a results value; and
storing the results value in a second register, wherein the results value specifies whether the write training operation was successful.
2. The computer-implemented method of claim 1 , further comprising:
determining that the first data pattern matches the second data pattern,
wherein the results value indicates a pass result.
3. The computer-implemented method of claim 1 , further comprising:
determining that the first data pattern does not match the second data pattern,
wherein the results value indicates a fail result.
4. The computer-implemented method of claim 1 , further comprising:
receiving a command to read the results value; and
transmitting the results value to an output pin of the memory device.
5. The computer-implemented method of claim 1 , further comprising: subsequent to transmitting the results value, initializing the second register to an initial value.
6. The computer-implemented method of claim 1 , wherein comparing the first data pattern with the second data pattern comprises performing an exclusive-or (XOR) operation on the first data pattern and the second data pattern.
7. The computer-implemented method of claim 6 , wherein the results value is based on an output of the XOR operation.
8. The computer-implemented method of claim 1 , wherein initializing the read/write memory comprises:
receiving a reset command from a memory controller; and
resetting a read pointer associated with the read/write memory.
9. The computer-implemented method of claim 1 , further comprising: subsequent to initializing the read/write memory, initializing the second register to an initial value.
10. The computer-implemented method of claim 9 , wherein the initial value comprises a fail status.
11. The computer-implemented method of claim 1 , further comprising:
receiving a data value from a memory controller via a command interface; and
storing the data value in the read/write memory.
12. The computer-implemented method of claim 1 , wherein the read/write memory comprises a first-in-first-out (FIFO) memory.
13. The computer-implemented method of claim 1 , wherein at least one of the first data pattern or the second data pattern comprises a pseudorandom bit sequence.
14. A system, comprising:
a memory controller; and
a memory device coupled to the memory controller, and that:
initializes a read/write memory on the memory device with a first data pattern based on a seed value stored in a first register;
receives, from the memory controller, a second data pattern on an input pin of the memory device;
compares the first data pattern with the second data pattern to generate a results value; and
stores the results value in a second register.
15. The system of claim 14 , where the memory device further:
determines that the first data pattern matches the second data pattern,
wherein the results value indicates a pass result.
16. The system of claim 14 , where the memory device further:
determines that the first data pattern does not match the second data pattern,
wherein the results value indicates a fail result.
17. The system of claim 14 , where the memory device further:
receives a command to read the results value; and
transmits the results value to an output pin of the memory device.
18. The system of claim 14 , where the memory device further, subsequent to transmitting the results value, initializes the second register to an initial value.
19. The system of claim 14 , wherein, when the memory device compares the first data pattern with the second data pattern, the memory device performs an exclusive-or (XOR) operation on the first data pattern and the second data pattern.
20. The system of claim 19 , wherein the results value is based on an output of the XOR operation.