IP Library › Granted Patent US 12,166,417
Granted Patent B2
US 12,166,417 · App. 17/554,991 · Granted Dec 10, 2024

Nonlinear current mirror for fast transient and low power regulator

Inventors: Jize Jiang (Singapore, SG); Hua Guan (San Diego, CA)
Assignee: QUALCOMM Incorporated
H02M3/158G05F1/445G05F1/573G05F1/575
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Quick Facts
Patent No.
US 12,166,417
App. No.
17/554,991
Granted
Dec 10, 2024
Kind
B2
Abstract

A power supply circuit and techniques for voltage regulation are described. Certain aspects provide a method of supplying power by a power supply circuit. The method generally includes: generating an output voltage based on a voltage at a Vin node via a first transistor having a gate coupled to a gate of a second transistor, wherein a source of the second transistor is coupled to the Vin node and wherein a drain of the second transistor is coupled a drain of a third transistor; and sourcing a current to the third transistor, wherein during a light load condition of the power supply circuit, the current varies based on the voltage at a Vout node of the power supply circuit, and during a heavy load condition of the power supply circuit, the current is limited based on a current threshold.

Claims (34)

1. A power supply circuit, comprising:

a first transistor having a source coupled to an input voltage (Vin) node and a drain coupled to an output voltage (Vout) node;

a second transistor having a source coupled to the Vin node;

a third transistor having a source coupled to a signal output of a current limiter circuit;

the current limiter circuit comprising:

a fifth transistor having a source coupled to the Vin node and a drain coupled to a current source; and

a sixth transistor having a source coupled to the Vin node and a drain coupled to the source of the third transistor, wherein a gate of the sixth transistor is coupled to the drain and a gate of the fifth transistor; and

a fourth transistor having a source coupled to a reference potential node, wherein a drain of the second transistor and a drain of the third transistor are coupled to a drain of the fourth transistor, and wherein a gate of the second transistor is coupled to a gate of the first transistor and a gate of the third transistor.

2. The power supply circuit of claim 1 , wherein, during a light load condition of the power supply circuit, the current limiter circuit and the third transistor are configured to provide a current that varies based on a voltage at the Vout node.

3. The power supply circuit of claim 1 , wherein, during a heavy load condition of the power supply circuit, the current limiter circuit and the third transistor are configured to provide a current that is limited based on a current threshold.

4. The power supply circuit of claim 3 , further comprising a current source configured to set the current threshold.

5. The power supply circuit of claim 1 , wherein:

the first transistor and the second transistor form a first current mirror; and

the first transistor and the third transistor form a second current mirror.

6. The power supply circuit of claim 1 , wherein:

a size of the first transistor and a size of the second transistor have a first ratio; and

the size of the first transistor and a size of the third transistor have a second ratio, the second ratio being less than the first ratio.

7. The power supply circuit of claim 1 , further comprising a control circuit comprising:

an amplifier having an output coupled to a gate of the fourth transistor; and

a feedback path coupled between the Vout node and an input of the amplifier.

8. The power supply circuit of claim 7 , wherein another input of the amplifier is coupled to a reference voltage (VREF) node.

9. The power supply circuit of claim 7 , further comprising a resistor-capacitor (RC) circuit coupled between an output of the amplifier and the reference potential node.

10. The power supply circuit of claim 1 , wherein the third transistor and the current limiter circuit are configured to source a constant current during heavy load conditions of the power supply circuit.

11. The power supply circuit of claim 1 , wherein, during light load conditions of the power supply circuit, the third transistor and the current limiter circuit are configured to operate as a diode coupled between the Vin node and the fourth transistor.

12. A power supply comprising:

a first transistor having a source coupled to an input voltage (Vin) node and a drain coupled to an output voltage (Vout) node;

a second transistor having a source coupled to the Vin node and a drain coupled to a drain-to-source voltage (Vds) clamp circuit;

a current limiter circuit;

a third transistor having a source coupled to a signal output of the current limiter circuit;

a fourth transistor having a source coupled to a reference potential node, wherein a drain of the second transistor and a drain of the third transistor are coupled to a drain of the fourth transistor, and wherein a gate of the second transistor is coupled to a gate of the first transistor and a gate of the third transistor; and

wherein the drain-to-source voltage (Vds) clamp circuit comprises:

a fifth transistor having a source coupled to the drain of the second transistor; and

an amplifier having a positive input coupled to the drain of the first transistor, a negative input coupled to the drain of the second transistor, and an output coupled to a gate of the fifth transistor.

13. The power supply circuit of claim 12 , further comprising a sixth transistor coupled between the drain of the third transistor and the drain of the fourth transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2022
From: JIANG, JIZE; GUAN, HUA
To: QUALCOMM INCORPORATED
Reel/Frame 058628/0010 →
Continuity (1)
Related Publication 20230198394A1 · Jun 22, 2023