IP Library › Granted Patent US 12,417,966
Granted Patent B2
US 12,417,966 · App. 17/555,106 · Granted Sep 16, 2025

IPD components having SiC substrates and devices and processes implementing the same

Inventors: Donald Farrell (Raleigh, NC); Marvin Marbell (Cary, NC); Jeremy Fisher (Raleigh, NC); Dan Namishia (Wake Forest, NC); Scott Sheppard (Chapel Hill, NC); Dan Etter (Durham, NC)
Assignee: MACOM Technology Solutions Holdings, Inc.
H01L23/49589H01L23/49575H01L23/645H01L23/647H01L24/85H01L24/48H01L2224/48245H10D30/47H10D30/65H10D62/8325H10D62/8503H10D84/83
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Quick Facts
Patent No.
US 12,417,966
App. No.
17/555,106
Granted
Sep 16, 2025
Kind
B2
Abstract

A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

Claims (44)

1. A transistor device, comprising:

a metal submount;

a transistor die arranged on said metal submount;

at least one integrated passive device (IPD) component comprising a substrate arranged on said metal submount; and

one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component,

wherein the substrate of the at least one integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate.

2. The transistor device according to claim 1 wherein the substrate comprises at least one via configured to make an electrical connection to the metal submount; and wherein the at least one integrated passive device (IPD) component is configured with at least one capacitor, resistor, and/or inductor.

3. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component comprises an intervening layer on the substrate of the at least one integrated passive device (IPD) component that comprises a Group III-nitride.

4. The transistor device according to claim 3 wherein the intervening layer comprises Gallium nitride (GaN).

5. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component comprises a dielectric layer, a top metal, a bottom metal, and a metallization layer on the substrate of the at least one integrated passive device (IPD) component.

6. The transistor device according to claim 5 wherein the at least one integrated passive device (IPD) component is configured to form a capacitor on the substrate of the at least one integrated passive device (IPD) component with the top metal and the bottom metal having the dielectric layer therebetween.

7. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component is configured to form an inductor on the substrate of the at least one integrated passive device (IPD) component.

8. The transistor device according to claim 7 wherein the inductor is implemented as a spiral shaped structure on the substrate of the at least one integrated passive device (IPD) component.

9. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component is configured with a plurality of interconnect pads; and wherein the at least one integrated passive device (IPD) component is a passive device.

10. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component comprises an interstage matching implementation.

11. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component comprises an output prematching implementation.

12. The transistor device according to claim 1 wherein the at least one integrated passive device (IPD) component comprises an input prematching implementation.

13. The transistor device according to claim 1 wherein the transistor die comprises one or multiple LDMOS transistor die.

14. The transistor device according to claim 1 wherein the transistor die comprises one or multiple GaN based HEMTs.

15. The transistor device according to claim 14 wherein at least one of the one or multiple GaN based HEMTs comprise a silicon carbide substrate.

16. The transistor device according to claim 1 wherein the transistor device comprises a plurality of the transistor die; and wherein the at least one integrated passive device (IPD) component is a passive device.

17. The transistor device according to claim 16 wherein the plurality of the transistor die are configured in a Doherty configuration.

18. A process for implementing a transistor device, comprising:

providing a metal submount;

arranging a transistor die on said metal submount;

arranging at least one integrated passive device (IPD) component comprising a substrate arranged on said metal submount; and

connecting one or more interconnects between the transistor die and the at least one integrated passive device (IPD) component,

wherein the substrate of the at least one integrated passive device (IPD) component comprises a silicon carbide (SiC) substrate.

19. The process for implementing a transistor device according to claim 18 further comprising forming at least one via in the substrate to make an electrical connection to the metal submount, wherein the at least one integrated passive device (IPD) component is configured with at least one capacitor, resistor, and/or inductor.

20. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component comprises an intervening layer on the substrate of the at least one integrated passive device (IPD) component that comprises a Group III-nitride.

21. The process for implementing a transistor device according to claim 20 wherein the intervening layer comprises Gallium nitride (GaN).

22. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component comprises a dielectric layer, a top metal, a bottom metal, and a metallization layer on the substrate of the at least one integrated passive device (IPD) component.

23. The process for implementing a transistor device according to claim 22 wherein the at least one integrated passive device (IPD) component is configured to form a capacitor on the substrate of the at least one integrated passive device (IPD) component with the top metal and the bottom metal having the dielectric layer therebetween.

24. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component is configured to form an inductor on the substrate of the at least one integrated passive device (IPD) component.

25. The process for implementing a transistor device according to claim 24 wherein the inductor is implemented as a spiral shaped structure on the substrate of the at least one integrated passive device (IPD) component.

26. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component is configured with a plurality of interconnect pads; and wherein the at least one integrated passive device (IPD) component is a passive device.

27. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component comprises an interstage matching implementation.

28. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component comprises an output prematching implementation.

29. The process for implementing a transistor device according to claim 18 wherein the at least one integrated passive device (IPD) component comprises an input prematching implementation.

30. The process for implementing a transistor device according to claim 18 wherein the transistor die comprises one or multiple LDMOS transistor die.

31. The process for implementing a transistor device according to claim 18 wherein the transistor die comprises one or multiple GaN based HEMTs.

32. The process for implementing a transistor device according to claim 31 wherein at least one of the one or multiple GaN based HEMTs comprise a silicon carbide substrate.

33. The process for implementing a transistor device according to claim 18 wherein the process for implementing a transistor device comprises a plurality of the transistor die; and wherein the at least one integrated passive device (IPD) component is a passive device.

34. The process for implementing a transistor device according to claim 33 wherein the plurality of the transistor die are configured in a Doherty configuration.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2023
From: WOLFSPEED, INC.
To: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
Reel/Frame 066236/0086 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2022
From: FARRELL, DONALD; MARBELL, MARVIN; FISHER, JEREMY; NAMISHIA, DAN; SHEPPARD, SCOTT; ETTER, DAN
To: WOLFSPEED, INC.
Reel/Frame 059470/0773 →
Continuity (1)
Related Publication 20230197587A1 · Jun 22, 2023
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