Ramp-based biasing and adjusting of access line voltage in a memory device
Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.
1. A device, comprising:
a plurality of access lines arranged in a grid;
a plurality of memory cells accessed via the plurality of access lines; and
biasing circuitry configured to bias a voltage supplied to a memory cell of the plurality of memory cells by biasing a voltage level of an access line of the plurality of access lines before transmission to the memory cell of the plurality of memory cells, wherein the biasing circuitry is configured to adjust the voltage level before the voltage level is supplied to the memory cell via the access line, the biasing circuitry comprises a bias transistor configured to control whether biasing is applied to the access line, and a ramp signal connected to a gate of the bias transistor at least partially determines a waveshape of the voltage level biasing the access line.
2. The device of claim 1 , wherein the biasing circuitry is configured to adjust the voltage level by adjusting a ramp rate based on a distance of the memory cell from a corresponding driver driving the memory cell.
3. The device of claim 1 , wherein the access lines comprise bitlines and wordlines, and the access line comprises a bitline or a wordline.
4. The device of claim 1 , wherein the biasing circuitry comprises a variable current source coupled to the ramp signal.
5. The device of claim 4 , further comprising a control circuit that is configured to set the variable current of the variable current source using a trim signal based at least in part on a location of the memory cell.
6. The device of claim 4 , wherein the biasing circuitry comprises a transistor configured to selectively couple and decouple the variable current source from the ramp signal.
7. The device of claim 4 , wherein the biasing circuitry comprises a voltage supply coupled to the variable current source on an opposite side of the variable current source from the ramp signal.
8. The device of claim 1 , wherein the biasing circuitry comprises a variable capacitor.
9. The device of claim 8 , wherein the variable capacitor is coupled between ground and the ramp signal.
10. The device of claim 9 , further comprising a control circuit that is configured to control the waveshape by changing the capacitance of the variable capacitor using a trim signal.