Systems and methods for an intelligent mapping of neural network weights and input data to an array of processing cores of an integrated circuit

1. A method of a transformed input data to an integrated circuit, the method comprising:

implementing a fast Fourier transform (FFT) of input data for processing on an integrated circuit;

generating an FFT matrix multiply based on implementing the FFT of the input data, the FFT matrix multiply comprising:

(1) a bit-reversed input array comprising N-bits of input, where N is a number of input bits in the bit-reversed input array; and

(2) a plurality of weight stages, wherein each weight stage of the plurality of weight stages comprises a distinct weight matrix;

at runtime:

storing one or more of the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array; and

executing, by the array of processing cores, the FFT matrix multiply including performing a plurality of matrix multiply computations between the plurality of weight stages and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.

2. The method according to claim 1 , further comprising:

generating a bit-reversed input bit index that indexes, in a corresponding manner, a sequence of input bits of an input array and a rearranged sequence of the inputs bits that define the bit-reversed input array.

3. The method according to claim 2 , further comprising:

generating the input bit mapping of each of the input bits of the bit-reversed input array to a processing core of the array of processing cores based on the bit-reversed input bit index.

4. The method according to claim 1 , further comprising:

generating the input bit mapping includes assigning a sequence of input bits of the bit-reversed input array to a memory location within a sequence of processing cores of the array of processing cores, wherein each input bit of the bit-reversed input array is assigned sequentially along the sequence of processing cores.

5. The method according to claim 4 , wherein

if a number of input bits in the sequence of input bits of the bit-reversed input array exceeds a number of processing cores in the sequence of processing cores, wrapping excess input bits of the bit-reversed input array around the array of processing cores by restarting a sequential assignment of the excess input bits along the sequence of processing cores.

6. The method according to claim 4 , wherein

if a number of input bits in the sequence of input bits of the bit-reversed input array exceeds a number of processing cores in the sequence of processing cores, storing multiple input bits of the bit-reversed input array onto one or more processing cores in the sequence of processing cores.

7. The method according to claim 1 , further comprising:

computing input bit movement instructions for on-processing core movements of the input bits of the bit-reversed input array for the plurality of matrix multiply computations associated with each of the plurality of weight stages, wherein the input bit movement instructions define one or more automatic transmissions of the input bits of the bit-reversed input array between memory circuits of distinct pairs of processing cores within the array of processing cores.

8. The method according to claim 7 , wherein

computing the input bit movement instructions includes:

identifying the input bits required for computations at each of the processing cores of the array of processing cores for each of the plurality of weight stages,

if a target input bit required for a computation is not stored locally at a target processing core, generating an input bit movement instruction that, when executed, causes the target input bit to transmit from a memory circuit of an originating processing core of the array of processing cores to a memory circuit of the target processing core of the array of processing cores.

9. The method according to claim 7 , further comprising:

executing the input bit movement instructions based on the performance of the plurality of matrix multiply computations.

10. The method according to claim 9 , wherein

executing the input bit movement instructions includes:

executing an input bit swap that exchanges a first input bit stored on a first processing core of the array of processing cores with a second input bit stored on a second processing core of the array of processing cores; and

storing the first input bit onto a memory circuit of the second processing core and storing the second input bit onto a memory circuit of the first processing core.

11. The method according to claim 9 , wherein

executing the input bit movement instructions includes:

executing an input bit core hop instruction that transmits an input bit stored on a memory of an originating processing core of the array of processing cores to a memory circuit of a destination processing core, wherein the input bit core hop instruction indicates a number of processing cores that the input bit moves either in a row or a column of processing cores.

12. The method according to claim 1 , wherein

executing the input bit movement instructions includes:

executing an input bit rotation instruction that internally transmits an input bit stored on a first memory circuit to a second memory circuit of a target processing core, wherein the internal transmission of the input bit includes a rotation of the input bit from the first memory circuit to the second memory circuit that is between zero and three-hundred sixty degrees.

13. A method of configuring an array of processors of an integrated circuit, the method comprising:

identifying a fast Fourier transform (FFT) matrix multiply of input data, wherein the FFT matrix multiply of the input data comprises a bit-reversed input array;

configuring the array of processing cores based on the bit-reversed input array, wherein the configuring the array of processing cores includes:

storing one or more of the input bits of the bit-reversed input array within memory circuits of distinct processing cores of an array of processing cores of the integrated circuit based on an input bit mapping that identifies a pre-determined storage location within the array of processing cores of each input bit of the bit-reversed input array; and

at runtime, executing by the array of processing cores the FFT matrix multiply including performing a plurality of matrix multiply computations between a plurality of weight stages of the FFT matrix multiply and the input bits of the bit-reversed input array stored within the memory circuits of the distinct processing cores.

14. The method according to claim 13 , further comprising:

generating the input bit mapping of each of the input bits of the bit-reversed input array based on a bit-reversed input bit index that indexes, in a corresponding manner, a sequence of input bits of an input array and a rearranged sequence of the inputs bits that define the bit-reversed input array.

15. The method according to claim 13 , further comprising:

generating the input bit mapping includes assigning a sequence of input bits of the bit-reversed input array to a memory location within a sequence of processing cores of the array of processing cores, wherein each input bit of the bit-reversed input array is assigned sequentially along the sequence of processing cores.

16. The method according to claim 13 , further comprising:

computing input bit movement instructions for on-processing core movements of the input bits of the bit-reversed input array for the plurality of matrix multiply computations associated with each of the plurality of weight stages, wherein the input bit movement instructions define one or more automatic transmissions of the input bits of the bit-reversed input array between memory circuits of distinct pairs of processing cores within the array of processing cores.