Display device and method of manufacturing the same

1. A method for manufacturing a display device, the method comprising:

forming an active pattern on a substrate;

forming a first transistor including a first gate electrode disposed in a first overlapping area of the active pattern where the first gate electrode overlaps the active pattern;

forming a first scan line disposed adjacent to the first gate electrode;

forming a first power voltage line including a first electrode portion overlapping the first gate electrode and a second electrode portion, which extends from the first electrode portion in a direction crossing the first scan line and overlaps the first scan line;

forming a first electrode pattern connected to the first gate electrode and overlapping the second electrode portion; and

forming an organic light-emitting layer on the substrate.

2. The method of claim 1 , further comprising:

forming a first insulation layer on the active pattern;

forming a second insulation layer on the first gate electrode;

forming a third insulation layer on the first power voltage line; and

forming a fourth insulation layer on the first electrode pattern,

wherein the first gate electrode is disposed on the first insulation layer, the first power voltage line is disposed on the second insulation layer, and the first electrode pattern is disposed on the third insulation layer.

3. The method of claim 1 , further comprising:

forming a second transistor including a second gate electrode in a second overlapping area of the active pattern where the first scan line overlaps the active pattern; and

forming a third transistor including a third gate electrode in a third overlapping area of the active pattern where the first scan line overlaps the active pattern,

wherein the first electrode pattern is connected to a third drain electrode of the third transistor.

4. The method of claim 1 , further comprising:

forming a data line, which crosses the first scan line; and

forming a second power voltage line, which crosses the first power voltage line and is connected to the first power voltage line.

5. The method of claim 1 , further comprising:

forming a second scan line parallel to the first scan line;

forming a fourth transistor including a fourth gate electrode disposed in a fourth overlapping area of the active pattern where the second scan line overlaps the active pattern; and

forming a seventh transistor including a seventh gate electrode disposed in a seventh overlapping area of the active pattern where the second scan line overlaps the active pattern.

6. The method of claim 5 , further comprising:

forming a light-emitting line disposed parallel to the first scan line;

forming a fifth transistor including a fifth gate electrode disposed in a fifth overlapping area of the active pattern where the light-emitting line overlaps the active pattern; and

forming a sixth transistor including a sixth gate electrode disposed in a sixth overlapping area of the active pattern where the light-emitting line overlaps the active pattern.

7. The method of claim 6 , further comprising:

forming an initializing voltage line disposed parallel to the first scan line;

forming a second electrode pattern, which connects the initializing voltage line to a seventh drain electrode of the seventh transistor; and

forming a third electrode pattern connected to a sixth drain electrode of the sixth transistor.