Embedded memory IC's with power supply droop circuitry coupled to ferroelectric capacitors
Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.
1. An integrated circuit (IC) die, comprising:
host circuitry comprising first transistors, wherein the host circuitry comprises power supply droop detection circuitry to detect supply voltage droop across power supply rails of the IC die;
an embedded memory array structure coupled to the host circuitry, wherein the embedded memory array structure comprises:
a plurality of first capacitors, each of the first capacitors comprising a first conductor and a second conductor with a ferroelectric material therebetween; and
a plurality of second transistors, wherein a first terminal of each of the second transistors is connected to the first conductor, a second terminal of the second transistors is coupled to one of a plurality of bitlines, and a third terminal of the second transistors is coupled to one of a plurality of wordlines; and
a plurality of second capacitors with conductors coupled to the power supply rails.
2. The IC die of claim 1 , wherein the second capacitors each comprise the ferroelectric material and are to be charged into a first polarization, and discharged into a second opposite polarization in response to supply voltage droop.
3. The IC die of claim 1 , wherein individual ones of the second capacitors are coupled to corresponding ones of third transistors, wherein a first terminal of each of the third transistors is connected to a first conductor of the second capacitors, a second terminal of each of the third transistors is connected to one of the supply rails, a third terminal of each of the third transistors is coupled to the droop detection circuitry and a second conductor of the second capacitors is coupled to another of the supply rails.
4. The IC die of claim 3 , wherein the first conductor of the second capacitors is over a dielectric material having undulating topography and first conductor conformally follows the undulating topography.
5. The IC die of claim 1 , further comprising one or more first levels of metallization over the first transistors, and wherein:
the memory array structure is over the first levels of metallization;
the plurality of second transistors is between the first capacitors and the first levels of metallization; and
the second capacitors are over the memory array structure.
6. The IC die of claim 1 , further comprising one or more first levels of metallization over the first transistors, and wherein:
the memory array structure is over the first levels of metallization;
the plurality of second transistors is between the first capacitors and the first levels of metallization; and
the second capacitors are co-planar with the first capacitors.
7. The IC die of claim 6 , wherein the first and second capacitors have substantially the same cylindrical structures.
8. The IC die of claim 1 , further comprising:
a substrate under the first transistors; and
a through-substrate via (TSV) extending through the substrate and adjacent to the first and second transistors and adjacent to the first and second capacitors.
9. The IC die of claim 8 , wherein the second capacitors are more proximal to the TSV than the first capacitors.
10. The IC die of claim 9 , wherein the second capacitors are more proximal to the TSV than the first capacitors.
11. The IC die of claim 10 , wherein the ferroelectric material has a relative permittivity over 25 and comprises predominantly Hf, O, and one or impurity dopants that comprise at least one of Si or Ge.
12. The IC die of claim 1 , further comprising:
a substrate under the first transistors; and
one or more first levels of metallization over the first transistors, and wherein:
the memory array structure is over the first levels of metallization;
the plurality of second transistors is between the first capacitors and the first levels of metallization; and
the second capacitors are embedded within the substrate.
13. The IC die of claim 1 , wherein a channel material of the second transistors comprises predominantly one or more metals and oxygen.
14. A system comprising:
an integrated circuit (IC) die, comprising:
host circuitry comprising first transistors, wherein the host circuitry comprises power supply droop detection circuitry to detect supply voltage droop across power supply rails of the IC die;
an embedded memory array structure coupled to the host circuitry, wherein the embedded memory array structure comprises:
a plurality of first capacitors, each of the first capacitors comprising a first conductor and a second conductor with a ferroelectric material therebetween; and
a plurality of second transistors, wherein a first terminal of each of the second transistors is connected to the first conductor, a second terminal of the second transistors is coupled to one of a plurality of bitlines, and a third terminal of the second transistors is coupled to one of a plurality of wordlines; and
a plurality of second capacitors with conductors switchably coupled to the power supply rails, wherein the second capacitors each comprise the ferroelectric material and are to be charged into a first polarization, and discharged into a second opposite polarization in response to supply voltage droop; and
a power supply coupled to power the IC die.
15. The system of claim 14 , wherein:
the IC die includes at least one of microprocessor core circuitry or floating point gate array (FPGA) circuitry.
16. A method of fabricating an integrated circuit (IC) die, the method comprising:
forming host integrated circuitry comprising plurality of first transistors over a substrate, wherein the host integrated circuitry comprises power supply droop detection circuitry to detect supply voltage droop across power supply rails of the IC die;
forming one or more first levels of metallization over the first transistors;
forming a memory array over the first levels of metallization, wherein forming the memory array comprises:
forming a plurality of second transistors;
forming a plurality of first conductor structures over the second transistors, wherein individual ones of the first conductor structures are coupled to a terminal of a corresponding one of the second transistors;
forming ferroelectric material upon a sidewall of the first conductor structures;
forming a plurality of second conductors upon a sidewall of the ferroelectric material; and
forming a plurality of capacitors comprising conductors switchably coupled to the power supply rails, wherein the capacitors each comprise the ferroelectric material and are to be charged into a first polarization, and discharged into a second opposite polarization in response to supply voltage droop.
17. The method of claim 16 , wherein forming the capacitors comprises forming the capacitors over the memory array by conformally depositing a first conductor of the capacitors over a dielectric material having undulating topography.
18. The method of claim 16 , wherein forming the capacitors comprises forming the capacitors co-planar with second capacitors within a region of the IC die proximal to a through-substrate via (TSV).
19. The method of claim 16 , wherein forming the capacitors comprises:
etching a via into the substrate;
laterally recessing first material layers of the substrate exposed within the via selectively over second material layers of the substrate exposed within the via; and
conformally depositing the conductors and the ferroelectric material into the via.
20. The method of claim 16 , wherein depositing the ferroelectric material comprises atomic layer deposition of a material comprising predominantly hafnium and oxygen.